Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934628AbeAHQOQ (ORCPT + 1 other); Mon, 8 Jan 2018 11:14:16 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36627 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756259AbeAHQOO (ORCPT ); Mon, 8 Jan 2018 11:14:14 -0500 X-Google-Smtp-Source: ACJfBou4j0gJdm5bWn9/+pbLy01uauvdRB+FmRJuMNmUYQnVhewFoFr9xL77hBRk+Gj+Bce3lhtbbA== Subject: Re: [PATCH v2 1/8] x86/feature: Detect the x86 IBRS feature to control Speculation To: Tim Chen , Thomas Gleixner , Andy Lutomirski , Linus Torvalds , Greg KH Cc: Dave Hansen , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , David Woodhouse , linux-kernel@vger.kernel.org References: From: Paolo Bonzini Message-ID: Date: Mon, 8 Jan 2018 17:14:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 06/01/2018 03:12, Tim Chen wrote: > cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature > IA32_SPEC_CTRL (0x48) > IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS) > > If IBRS is set, near returns and near indirect jumps/calls will not allow > their predicted target address to be controlled by code that executed in > a less privileged prediction mode before the IBRS mode was last written > with a value of 1 or on another logical processor so long as all RSB > entries from the previous less privileged prediction mode are overwritten. > > * Thus a near indirect jump/call/return may be affected by code in a > less privileged prediction mode that executed AFTER IBRS mode was last > written with a value of 1 > > * There is no need to clear IBRS before writing it with a value of > 1. Unconditionally writing it with a value of 1 after the prediction > mode change is sufficient > > * Note: IBRS is not required in order to isolate branch predictions for > SMM or SGX enclaves > > * Code executed by a sibling logical processor cannot control indirect > jump/call/return predicted target when IBRS is set > > * SMEP will prevent supervisor mode using RSB entries filled by user code; > this can reduce the need for software to overwrite RSB entries > > CPU performance could be reduced when running with IBRS set. > > Signed-off-by: Tim Chen KVM also needs STIBP, can you please add it, or perhaps split cpuid(7,0).edx out to its own feature word? Thanks, Paolo > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/msr-index.h | 4 ++++ > arch/x86/kernel/cpu/scattered.c | 1 + > tools/arch/x86/include/asm/cpufeatures.h | 1 + > 4 files changed, 7 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 07cdd17..5ee0737 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -209,6 +209,7 @@ > #define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ > > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ > +#define X86_FEATURE_SPEC_CTRL ( 7*32+19) /* Control Speculation Control */ > > /* Virtualization flags: Linux defined, word 8 */ > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 34c4922..f881add 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -42,6 +42,10 @@ > #define MSR_PPIN_CTL 0x0000004e > #define MSR_PPIN 0x0000004f > > +#define MSR_IA32_SPEC_CTRL 0x00000048 > +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0) > +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0) > + > #define MSR_IA32_PERFCTR0 0x000000c1 > #define MSR_IA32_PERFCTR1 0x000000c2 > #define MSR_FSB_FREQ 0x000000cd > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index 05459ad..bc50c40 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -24,6 +24,7 @@ static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_INTEL_PT, CPUID_EBX, 25, 0x00000007, 0 }, > { X86_FEATURE_AVX512_4VNNIW, CPUID_EDX, 2, 0x00000007, 0 }, > { X86_FEATURE_AVX512_4FMAPS, CPUID_EDX, 3, 0x00000007, 0 }, > + { X86_FEATURE_SPEC_CTRL, CPUID_EDX, 26, 0x00000007, 0 }, > { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, > { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, > { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, > diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h > index 800104c..5e56275 100644 > --- a/tools/arch/x86/include/asm/cpufeatures.h > +++ b/tools/arch/x86/include/asm/cpufeatures.h > @@ -208,6 +208,7 @@ > #define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */ > > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ > +#define X86_FEATURE_SPEC_CTRL ( 7*32+19) /* Control Speculation Control */ > > /* Virtualization flags: Linux defined, word 8 */ > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ >