Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935416AbeAHRCs (ORCPT + 1 other); Mon, 8 Jan 2018 12:02:48 -0500 Received: from mga09.intel.com ([134.134.136.24]:48850 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935401AbeAHRCo (ORCPT ); Mon, 8 Jan 2018 12:02:44 -0500 X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,330,1511856000"; d="scan'208";a="8771183" Date: Mon, 8 Jan 2018 22:36:55 +0530 From: Vinod Koul To: Appana Durga Kedareswara Rao Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , "lars@metafoo.de" , "akinobu.mita@gmail.com" , "joabreu@synopsys.com" , "mike.looijmans@topic.nl" , "kedare06@gmail.com" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly Message-ID: <20180108170655.GJ18649@localhost> References: <1514961731-1916-1-git-send-email-appanad@xilinx.com> <1514961731-1916-2-git-send-email-appanad@xilinx.com> <20180108103845.GE18649@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Mon, Jan 08, 2018 at 10:52:01AM +0000, Appana Durga Kedareswara Rao wrote: > Hi Vinod, > > Thanks for the review.... > > >> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct > >xilinx_dma_device *xdev, > >> chan->direction = DMA_MEM_TO_DEV; > >> chan->id = chan_id; > >> chan->tdest = chan_id; > >> + xdev->common.directions = BIT(DMA_MEM_TO_DEV); > >> > >> chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2415,6 > >> +2416,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, > >> chan->direction = DMA_DEV_TO_MEM; > >> chan->id = chan_id; > >> chan->tdest = chan_id - xdev->nr_channels; > >> + xdev->common.directions |= BIT(DMA_DEV_TO_MEM); > >> > >> chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; > >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ - > >2629,6 > >> +2631,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) > >> dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); > >> } > >> > >> + xdev->common.dst_addr_widths = BIT(addr_width / 8); > >> + xdev->common.src_addr_widths = BIT(addr_width / 8); > > > >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? What is value > >of addr_width here typically? Usually controllers can support different widths and > >this is a surprise that you support only one value > > Controller supports address width of 32 and 64. Then this should have both 32 and 64 values here > addr_width typical values are 32-bit or 64-bit . > Here addr_width is device-tree parameter... > my understanding of src_addr_widths/dst_addr_widths is, it is a bit mask of the > address with in bytes that DMA supports, please correct if my understanding is wrong. > > Regards, > Kedar. > > > > >-- > >~Vinod -- ~Vinod