Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754330AbeAHRcl (ORCPT + 1 other); Mon, 8 Jan 2018 12:32:41 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42826 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754288AbeAHRcj (ORCPT ); Mon, 8 Jan 2018 12:32:39 -0500 From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Will Deacon Subject: [PATCH v3 00/13] arm64 kpti hardening and variant 2 workarounds Date: Mon, 8 Jan 2018 17:32:25 +0000 Message-Id: <1515432758-26440-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Hi all, This is version three of the patches previously posted here: v1: http://lists.infradead.org/pipermail/linux-arm-kernel/2018-January/551838.html v2: http://lists.infradead.org/pipermail/linux-arm-kernel/2018-January/552085.html Changes since v2: * Fix typo in comment * Include Falkor hardening from Shanker * Add ThunderX2 MIDRs (subsequent patches under review) * Avoid applying hardening from preemtible context * Fix stack offsets in hyp SMC call Cheers, Will --->8 Jayachandran C (1): arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Marc Zyngier (3): arm64: Move post_ttbr_update_workaround to C code arm64: KVM: Use per-CPU vector when BP hardening is enabled arm64: KVM: Make PSCI_VERSION a fast path Shanker Donthineni (1): arm64: Implement branch predictor hardening for Falkor Will Deacon (8): arm64: use RET instruction for exiting the trampoline arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry arm64: Take into account ID_AA64PFR0_EL1.CSV3 arm64: cpufeature: Pass capability structure to ->enable callback drivers/firmware: Expose psci_get_version through psci_ops structure arm64: Add skeleton to harden the branch predictor against aliasing attacks arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 arm64: Implement branch predictor hardening for affected Cortex-A CPUs arch/arm/include/asm/kvm_mmu.h | 10 +++ arch/arm64/Kconfig | 30 +++++-- arch/arm64/include/asm/assembler.h | 13 --- arch/arm64/include/asm/cpucaps.h | 4 +- arch/arm64/include/asm/cputype.h | 7 ++ arch/arm64/include/asm/kvm_asm.h | 2 + arch/arm64/include/asm/kvm_mmu.h | 38 +++++++++ arch/arm64/include/asm/mmu.h | 37 +++++++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/Makefile | 4 + arch/arm64/kernel/bpi.S | 87 ++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 161 +++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 13 ++- arch/arm64/kernel/entry.S | 19 ++++- arch/arm64/kvm/hyp/entry.S | 12 +++ arch/arm64/kvm/hyp/switch.c | 25 +++++- arch/arm64/mm/context.c | 11 +++ arch/arm64/mm/fault.c | 17 ++++ arch/arm64/mm/proc.S | 3 +- drivers/firmware/psci.c | 2 + include/linux/psci.h | 1 + virt/kvm/arm/arm.c | 8 +- 22 files changed, 474 insertions(+), 32 deletions(-) create mode 100644 arch/arm64/kernel/bpi.S -- 2.1.4