Subject: Re: [tip:x86/pti] x86/cpu/AMD: Use LFENCE_RDTSC instead of
 MFENCE_RDTSC
To: Paolo Bonzini <pbonzini@redhat.com>,
        "Dr. David Alan Gilbert" <dgilbert@redhat.com>,
        Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, bp@alien8.de,
        dwmw@amazon.co.uk, gregkh@linux-foundation.org, pjt@google.com,
        mingo@kernel.org, linux-kernel@vger.kernel.org, hpa@zytor.com,
        tim.c.chen@linux.intel.com, torvalds@linux-foundation.org,
        peterz@infradead.org, dave.hansen@intel.com,
        linux-tip-commits@vger.kernel.org
References: <20180105160756.23786.4220.stgit@tlendack-t1.amdoffice.net>
 <tip-0bf17c102177d5da9363bf8b1e4704b9996d5079@git.kernel.org>
 <alpine.DEB.2.20.1801081105120.1735@nanos>
 <1b179b8b-6cc8-d736-81dc-2445be4baf02@citrix.com>
 <alpine.DEB.2.20.1801081208500.1735@nanos>
 <4d9a1f0d-a401-3f0f-9ee2-dd42f4b4716a@amd.com>
 <929a34a1-e3bc-b1c8-4c71-196610c0d02a@citrix.com>
 <20180108164803.GF2462@work-vm>
 <0be27b7e-7285-b23b-7eda-55a70338d16c@redhat.com>
From: Tom Lendacky <thomas.lendacky@amd.com>
Message-ID: <00e18fcc-6a56-0d39-e3c8-7f9a1ffcc260@amd.com>
Date: Mon, 8 Jan 2018 11:39:23 -0600
User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101
 Thunderbird/52.5.2
MIME-Version: 1.0
In-Reply-To: <0be27b7e-7285-b23b-7eda-55a70338d16c@redhat.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 8bit
SpamDiagnosticOutput: 1:99
SpamDiagnosticMetadata: NSPM
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2018 17:39:27.8484 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 6537a3bb-cb5f-4378-3890-08d556bec589
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1151
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Return-Path: <linux-kernel-owner@vger.kernel.org>

On 1/8/2018 11:01 AM, Paolo Bonzini wrote:
> On 08/01/2018 17:48, Dr. David Alan Gilbert wrote:
>>> If your hypervisor is lying to you about the primary family, then all
>>> bets are off.  I don't expect there will be any production systems doing
>>> this.
>> It's not that an unusual thing to do on qemu/kvm - to specify the lowest
>> common denominator of the set of CPUs in your data centre (for any one
>> vendor); it does tend to get some weird combinations.
> 
> Agreed.  But on a hypervisor we pretty much know that:
> 
> - the MSR_AMD64_DE_CFG doesn't exist unless you have a fix

Not sure what you mean by this...  the MSR exists today on many families.

Thanks,
Tom

> 
> - setting the MSR_AMD64_DE_CFG bit to 1 if you have a fix can be done
> independent of the family
> 
> So all KVM needs is a X86_FEATURE_LFENCE_SERIALIZE, it doesn't matter if
> it's because of the family or because Linux has set MSR_F10H_DE_CFG.
> The guest will either try setting the MSR bit and #GP, or it will find
> it already set and do nothing.
> 
> Of course no code for this has been written yet.
> 
> Paolo
>