Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754496AbeAHRko (ORCPT + 1 other); Mon, 8 Jan 2018 12:40:44 -0500 Received: from mail-co1nam03on0076.outbound.protection.outlook.com ([104.47.40.76]:29496 "EHLO NAM03-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754125AbeAHRk1 (ORCPT ); Mon, 8 Jan 2018 12:40:27 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jayachandran.Nair@cavium.com; Date: Mon, 8 Jan 2018 09:40:17 -0800 From: Jayachandran C To: Marc Zyngier Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, labbott@redhat.com, christoffer.dall@linaro.org Subject: Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3 Message-ID: <20180108174016.GB180149@jc-sabre> References: <1515157961-20963-4-git-send-email-will.deacon@arm.com> <20180108072253.GA178830@jc-sabre> <9bc1f137-d78c-e46e-e1bc-f49160d5f289@arm.com> MIME-Version: 1.0 Content-Type: text/plain; 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> >> > >> static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { > >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), > >> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), > >> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), > >> S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), > >> @@ -851,6 +852,8 @@ static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ > >> static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, > >> int __unused) > >> { > >> + u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); > >> + > >> /* Forced on command line? */ > >> if (__kpti_forced) { > >> pr_info_once("kernel page table isolation forced %s by command line option\n", > >> @@ -862,7 +865,9 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, > >> if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) > >> return true; > >> > >> - return false; > >> + /* Defer to CPU feature registers */ > >> + return !cpuid_feature_extract_unsigned_field(pfr0, > >> + ID_AA64PFR0_CSV3_SHIFT); > > > > If I read this correctly, this enables KPTI on all processors without the CSV3 > > set (which seems to be a future capability). > > > > Turning on KPTI has a small but significant overhead, so I think we should turn > > it off on processors that are not vulnerable to CVE-2017-5754. Can we add something > > like this: > > > > --->8 > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index 19ed09b..202b037 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -862,6 +862,13 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, > > return __kpti_forced > 0; > > } > > > > + /* Don't force KPTI for CPUs that are not vulnerable */ > > + switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { > > + case MIDR_CAVIUM_THUNDERX2: > > + case MIDR_BRCM_VULCAN: > > + return false; > > + } > > + > > /* Useful for KASLR robustness */ > > if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) > > return true; > > > > KPTI is also an improvement for KASLR. Why would you deprive a user of > the choice to further secure their system? The user has a choice with kpti= at the kernel command line, so we are not depriving the user of a choice. KASLR is expected to be enabled by distributions, and KPTI will be enabled by default as well. On systems that are not vulnerable to variant 3, this is an unnecessary overhead. JC