Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755201AbeAHSI5 (ORCPT + 1 other); Mon, 8 Jan 2018 13:08:57 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44398 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755036AbeAHSIy (ORCPT ); Mon, 8 Jan 2018 13:08:54 -0500 X-Google-Smtp-Source: ACJfBovCVZXBxR8BHqiA090VwLCgku/RRAb/JFKHEon5u6ah+CqxJnLCECADBfR7KzCLI0ehfW31+g== From: Paolo Bonzini To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: jmattson@google.com, aliguori@amazon.com, thomas.lendacky@amd.com, dwmw@amazon.co.uk, bp@alien8.de Subject: [PATCH 2/7] x86/msr: add definitions for indirect branch predictor MSRs Date: Mon, 8 Jan 2018 19:08:40 +0100 Message-Id: <1515434925-10250-3-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515434925-10250-1-git-send-email-pbonzini@redhat.com> References: <1515434925-10250-1-git-send-email-pbonzini@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: KVM will start using them soon. Signed-off-by: Paolo Bonzini --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 03ffde6217d0..ec08f1d8d39b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -39,6 +39,11 @@ /* Intel MSRs. Some also available on other CPUs */ +#define MSR_IA32_SPEC_CTRL 0x00000048 + +#define MSR_IA32_PRED_CMD 0x00000049 +#define FEATURE_SET_IBPB (1UL << 0) + #define MSR_PPIN_CTL 0x0000004e #define MSR_PPIN 0x0000004f -- 1.8.3.1