Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756043AbeAHSwt (ORCPT + 1 other); Mon, 8 Jan 2018 13:52:49 -0500 Received: from mail-it0-f66.google.com ([209.85.214.66]:38449 "EHLO mail-it0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755689AbeAHSwr (ORCPT ); Mon, 8 Jan 2018 13:52:47 -0500 X-Google-Smtp-Source: ACJfBouMSHPMnagDXy1JnUZAswwC8mc6tGpB135oGDwXynsVgDGb1GA9SBAeiPLnWjmHdTqHqOOhFDDwyOcxOyJTwIc= MIME-Version: 1.0 In-Reply-To: <20180108183529.GD17375@char.us.oracle.com> References: <1515434925-10250-1-git-send-email-pbonzini@redhat.com> <1515434925-10250-3-git-send-email-pbonzini@redhat.com> <20180108183529.GD17375@char.us.oracle.com> From: Jim Mattson Date: Mon, 8 Jan 2018 10:52:46 -0800 Message-ID: Subject: Re: [PATCH 2/7] x86/msr: add definitions for indirect branch predictor MSRs To: Konrad Rzeszutek Wilk Cc: Paolo Bonzini , LKML , kvm list , aliguori@amazon.com, Tom Lendacky , dwmw@amazon.co.uk, bp@alien8.de Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: I don't really understand the organization of this file, but I put these MSRs in the /* Intel defined MSRs. */ block, between MSR_IA32_TSC_ADJUST and MSR_IA32_BNDCFGS. On Mon, Jan 8, 2018 at 10:35 AM, Konrad Rzeszutek Wilk wrote: > On Mon, Jan 08, 2018 at 07:08:40PM +0100, Paolo Bonzini wrote: >> KVM will start using them soon. > > Perhaps include a bit of description? >> >> Signed-off-by: Paolo Bonzini >> --- >> arch/x86/include/asm/msr-index.h | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h >> index 03ffde6217d0..ec08f1d8d39b 100644 >> --- a/arch/x86/include/asm/msr-index.h >> +++ b/arch/x86/include/asm/msr-index.h >> @@ -39,6 +39,11 @@ >> >> /* Intel MSRs. Some also available on other CPUs */ >> >> +#define MSR_IA32_SPEC_CTRL 0x00000048 >> + >> +#define MSR_IA32_PRED_CMD 0x00000049 >> +#define FEATURE_SET_IBPB (1UL << 0) >> + >> #define MSR_PPIN_CTL 0x0000004e >> #define MSR_PPIN 0x0000004f >> >> -- >> 1.8.3.1 >> >>