From: Tom Lendacky <thomas.lendacky@amd.com>
Subject: [PATCH v2 0/2] x86/cpu/AMD: Make LFENCE a serializing instruction
 on AMD
To: x86@kernel.org, linux-kernel@vger.kernel.org
Cc: Peter Zijlstra <peterz@infradead.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Dan Williams <dan.j.williams@intel.com>,
        Dave Hansen <dave.hansen@intel.com>,
        Borislav Petkov <bp@alien8.de>,
        Thomas Gleixner <tglx@linutronix.de>,
        Tim Chen <tim.c.chen@linux.intel.com>,
        Greg Kroah-Hartman <gregkh@linux-foundation.org>,
        David Woodhouse <dwmw@amazon.co.uk>,
        Paul Turner <pjt@google.com>
Date: Mon, 08 Jan 2018 16:09:12 -0600
Message-ID: <20180108220912.12580.82330.stgit@tlendack-t1.amdoffice.net>
User-Agent: StGit/0.17.1-dirty
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
SpamDiagnosticOutput: 1:99
SpamDiagnosticMetadata: NSPM
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2018 22:09:15.6742 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: fa304e24-867b-4d93-9883-08d556e47569
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1151
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Return-Path: <linux-kernel-owner@vger.kernel.org>

To aid in speculation control, the LFENCE instruction will be turned into
a serializing instruction. There is less performance impact using LFENCE
in this way compared to MFENCE.

With LFENCE now being a serializing instruction, it can be also used in
rdtsc_ordered() in preference to MFENCE_RDTSC.  Since the kernel could
be running under a hypervisor that does not allow writing to that MSR,
it must be first verified that the write was successful before setting
the LFENCE_RDTSC feature.

The following patches are included in this series:
- Make LFENCE a serializing instruction on AMD
- Use LFENCE_RDTSC in preference to MFENCE_RDTSC on AMD

This patch series is based on tip:x86/pti.

---

Changes from v1:
- Add a check verifying the MSR was actually updated
- Remove the third patch that eliminates the MFENCE_RDTSC feature
  (since the feature is still needed)
- Adding Dan Williams to the cc since this will impact nospec_barrier(),
  which will require an alternative_2 to add an MFENCE instruction with
  an MFENCE_RDTSC check

Tom Lendacky (2):
      x86/cpu/AMD: Make LFENCE a serializing instruction
      x86/cpu/AMD: Use LFENCE_RDTSC in preference to MFENCE_RDTSC


 arch/x86/include/asm/msr-index.h |    3 +++
 arch/x86/kernel/cpu/amd.c        |   27 +++++++++++++++++++++++++--
 2 files changed, 28 insertions(+), 2 deletions(-)

-- 
Tom Lendacky