Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757080AbeAHWcT (ORCPT + 1 other); Mon, 8 Jan 2018 17:32:19 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:50625 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754900AbeAHWcS (ORCPT ); Mon, 8 Jan 2018 17:32:18 -0500 From: Chris Packham To: jlu@pengutronix.de, linux@armlinux.org.uk, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Chris Packham , Mauro Carvalho Chehab Subject: [PATCH 3/3] EDAC: armada_xp: Add support for more SoCs Date: Tue, 9 Jan 2018 11:31:58 +1300 Message-Id: <20180108223158.21930-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180108223158.21930-1-chris.packham@alliedtelesis.co.nz> References: <20180108223158.21930-1-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The Armada 38x and other integrated SoCs use a reduced pin count so the width of the SDRAM interface is smaller than the Armada XP SoCs. This means that the definition of "full" and "half" width is reduced from 64/32 to 32/16. Signed-off-by: Chris Packham --- drivers/edac/armada_xp_edac.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c index cb9173b30aa9..40cef261e61b 100644 --- a/drivers/edac/armada_xp_edac.c +++ b/drivers/edac/armada_xp_edac.c @@ -347,6 +347,11 @@ static int armada_xp_mc_edac_probe(struct platform_device *pdev) armada_xp_mc_edac_read_config(mci); + /* These SoCs have a reduced width bus */ + if (of_machine_is_compatible("marvell,armada380") || + of_machine_is_compatible("marvell,armadaxp-98dx3236")) + drvdata->width /= 2; + /* configure SBE threshold */ /* it seems that SBEs are not captured otherwise */ writel(1 << SDRAM_ERR_CTRL_ERR_THR_OFFSET, -- 2.15.1