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From: Dan Williams <dan.j.williams@intel.com>
Date: Mon, 8 Jan 2018 14:34:31 -0800
Message-ID: <CAPcyv4htdFDS16MGAxwy5U6zYv+tw2_yntTbnQ0fwXxrVvGAWw@mail.gmail.com>
Subject: Re: [PATCH v2 0/2] x86/cpu/AMD: Make LFENCE a serializing instruction
 on AMD
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: X86 ML <x86@kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Dave Hansen <dave.hansen@intel.com>,
        Borislav Petkov <bp@alien8.de>,
        Thomas Gleixner <tglx@linutronix.de>,
        Tim Chen <tim.c.chen@linux.intel.com>,
        Greg Kroah-Hartman <gregkh@linux-foundation.org>,
        David Woodhouse <dwmw@amazon.co.uk>,
        Paul Turner <pjt@google.com>
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Sender: linux-kernel-owner@vger.kernel.org

On Mon, Jan 8, 2018 at 2:09 PM, Tom Lendacky <thomas.lendacky@amd.com> wrote:
> To aid in speculation control, the LFENCE instruction will be turned into
> a serializing instruction. There is less performance impact using LFENCE
> in this way compared to MFENCE.
>
> With LFENCE now being a serializing instruction, it can be also used in
> rdtsc_ordered() in preference to MFENCE_RDTSC.  Since the kernel could
> be running under a hypervisor that does not allow writing to that MSR,
> it must be first verified that the write was successful before setting
> the LFENCE_RDTSC feature.
>
> The following patches are included in this series:
> - Make LFENCE a serializing instruction on AMD
> - Use LFENCE_RDTSC in preference to MFENCE_RDTSC on AMD
>
> This patch series is based on tip:x86/pti.
>
> ---
>
> Changes from v1:
> - Add a check verifying the MSR was actually updated
> - Remove the third patch that eliminates the MFENCE_RDTSC feature
>   (since the feature is still needed)
> - Adding Dan Williams to the cc since this will impact nospec_barrier(),
>   which will require an alternative_2 to add an MFENCE instruction with
>   an MFENCE_RDTSC check

Thanks Tom, I'll include this in the next posting of the variant-1 patch series.