Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755028AbeAIAye (ORCPT + 1 other); Mon, 8 Jan 2018 19:54:34 -0500 Received: from terminus.zytor.com ([65.50.211.136]:34343 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753195AbeAIAyd (ORCPT ); Mon, 8 Jan 2018 19:54:33 -0500 Date: Mon, 8 Jan 2018 16:48:48 -0800 From: tip-bot for Tom Lendacky Message-ID: Cc: hpa@zytor.com, dave.hansen@intel.com, thomas.lendacky@amd.com, tglx@linutronix.de, bp@alien8.de, peterz@infradead.org, torvalds@linux-foundation.org, dan.j.williams@intel.com, gregkh@linux-foundation.org, dwmw@amazon.co.uk, mingo@kernel.org, pjt@google.com, tim.c.chen@linux.intel.com, bp@suse.de, linux-kernel@vger.kernel.org Reply-To: peterz@infradead.org, torvalds@linux-foundation.org, dan.j.williams@intel.com, gregkh@linux-foundation.org, thomas.lendacky@amd.com, hpa@zytor.com, dave.hansen@intel.com, tglx@linutronix.de, bp@alien8.de, tim.c.chen@linux.intel.com, bp@suse.de, linux-kernel@vger.kernel.org, dwmw@amazon.co.uk, mingo@kernel.org, pjt@google.com In-Reply-To: <20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net> References: <20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/pti] x86/cpu/AMD: Make LFENCE a serializing instruction Git-Commit-ID: e4d0e84e490790798691aaa0f2e598637f1867ec X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Commit-ID: e4d0e84e490790798691aaa0f2e598637f1867ec Gitweb: https://git.kernel.org/tip/e4d0e84e490790798691aaa0f2e598637f1867ec Author: Tom Lendacky AuthorDate: Mon, 8 Jan 2018 16:09:21 -0600 Committer: Thomas Gleixner CommitDate: Tue, 9 Jan 2018 01:43:10 +0100 x86/cpu/AMD: Make LFENCE a serializing instruction To aid in speculation control, make LFENCE a serializing instruction since it has less overhead than MFENCE. This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG). Some families that support LFENCE do not have this MSR. For these families, the LFENCE instruction is already serializing. Signed-off-by: Tom Lendacky Signed-off-by: Thomas Gleixner Reviewed-by: Reviewed-by: Borislav Petkov Cc: Peter Zijlstra Cc: Tim Chen Cc: Dave Hansen Cc: Borislav Petkov Cc: Dan Williams Cc: Linus Torvalds Cc: Greg Kroah-Hartman Cc: David Woodhouse Cc: Paul Turner Link: https://lkml.kernel.org/r/20180108220921.12580.71694.stgit@tlendack-t1.amdoffice.net --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ab02261..1e7d710 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -352,6 +352,8 @@ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL #define FAM10H_MMIO_CONF_BASE_SHIFT 20 #define MSR_FAM10H_NODE_ID 0xc001100c +#define MSR_F10H_DECFG 0xc0011029 +#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 /* K8 MSRs */ #define MSR_K8_TOP_MEM1 0xc001001a diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bcb75dc..5b438d8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -829,6 +829,16 @@ static void init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_K8); if (cpu_has(c, X86_FEATURE_XMM2)) { + /* + * A serializing LFENCE has less overhead than MFENCE, so + * use it for execution serialization. On families which + * don't have that MSR, LFENCE is already serializing. + * msr_set_bit() uses the safe accessors, too, even if the MSR + * is not present. + */ + msr_set_bit(MSR_F10H_DECFG, + MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); + /* MFENCE stops RDTSC speculation */ set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); }