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Date: Tue, 9 Jan 2018 10:18:58 +0530
From: Vinod Koul <vinod.koul@intel.com>
To: Appana Durga Kedareswara Rao <appanad@xilinx.com>
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Subject: Re: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly
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On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao wrote:
> Hi,
> 
> <Snip>
> >> >> +	xdev->common.dst_addr_widths = BIT(addr_width / 8);
> >> >> +	xdev->common.src_addr_widths = BIT(addr_width / 8);
> >> >
> >> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers?
> >> >What is value of addr_width here typically? Usually controllers can
> >> >support different widths and this is a surprise that you support only
> >> >one value
> >>
> >> Controller supports address width of 32 and 64.
> >
> >Then this should have both 32 and 64 values here
> 
> Address width is configurable parameter at the h/w level.
> Since this IP is a soft IP user can create a design with either 
> 32-bit or 64-bit address configuration. 

and not both right?

> Currently we are reading this configuration through device-tree (xlnx, addr-width property) 
> https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/slave-dma.git/tree/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt#n19
> Based on the h/w configuration setting the dst_addr_widths/src_addr_widths variables in this patch.
> Please let me know if you are still not clear with my explanation will explain in detail... 
> 
> Regards,
> Kedar.
> 
> >
> >> addr_width typical values are 32-bit or 64-bit .
> >> Here addr_width is device-tree parameter...
> >> my understanding of src_addr_widths/dst_addr_widths is, it is a bit
> >> mask of the address with in bytes that DMA supports, please correct if my
> >understanding is wrong.
> >>
> >> Regards,
> >> Kedar.
> >>
> >> >
> >> >--
> >> >~Vinod
> >
> >--
> >~Vinod

-- 
~Vinod