Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753552AbeAIKDj (ORCPT + 1 other); Tue, 9 Jan 2018 05:03:39 -0500 Received: from mail-eopbgr00077.outbound.protection.outlook.com ([40.107.0.77]:29872 "EHLO EUR02-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753227AbeAIKDb (ORCPT ); Tue, 9 Jan 2018 05:03:31 -0500 From: Anson Huang To: Dong Aisheng CC: =?iso-8859-2?Q?Horia_Geant=E3?= , Aymen Sghaier , "herbert@gondor.apana.org.au" , "davem@davemloft.net" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "kernel@pengutronix.de" , Fabio Estevam , "linux@armlinux.org.uk" , "mturquette@baylibre.com" , "sboyd@codeaurora.org" , Adriana Reus , "stefan@agner.ch" , "linux-crypto@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" , dl-linux-imx Subject: RE: [PATCH V3 2/2] ARM: dts: imx7s: add snvs rtc clock Thread-Topic: [PATCH V3 2/2] ARM: dts: imx7s: add snvs rtc clock Thread-Index: AQHTiS7fwsdElgOKwEGvPBlwwCj4GaNrTuLA Date: Tue, 9 Jan 2018 10:03:18 +0000 Message-ID: References: <1515489651-13488-1-git-send-email-Anson.Huang@nxp.com> <1515489651-13488-2-git-send-email-Anson.Huang@nxp.com> <20180109094716.GH26312@b29396-OptiPlex-7040> In-Reply-To: <20180109094716.GH26312@b29396-OptiPlex-7040> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; x-originating-ip: [199.59.231.64] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM3PR04MB324;7:dbKVYDU95ijfyhDJKxCPzNFAlk0M84p7jFbVfvwpCLNhtTCld/N2oskdI6Nfpe0Xca26C+wbAK2H6PqPF+Dheq1d5xrNfrLD6D4Gl11oc+NUEZAYhsF7A+6Zr9rN+l3OJ12GCSI63OcsMHDDZlOMCE8uKCoxcPXmesugLplAC42LE68Susp8H8qqTePYbXs/p37lT4VOSooEigAGQ1mdoNTjumBj7HodtPxpTocM7vX1ugTwvjOnRnJpCME+g8cH x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 151c983a-663b-4352-d488-08d55748359e x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(48565401081)(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(5600026)(4604075)(3008032)(2017052603307)(7153060)(7193020);SRVR:AM3PR04MB324; x-ms-traffictypediagnostic: AM3PR04MB324: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(9452136761055)(185117386973197)(85827821059158)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040470)(2401047)(8121501046)(5005006)(3231023)(944501075)(3002001)(10201501046)(93006095)(93001095)(6055026)(6041268)(20161123564045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123560045)(6072148)(201708071742011);SRVR:AM3PR04MB324;BCL:0;PCL:0;RULEID:(100000803101)(100110400095);SRVR:AM3PR04MB324; x-forefront-prvs: 0547116B72 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(376002)(396003)(39380400002)(366004)(39860400002)(346002)(189003)(199004)(377424004)(24454002)(13464003)(6246003)(81156014)(66066001)(2906002)(5250100002)(9686003)(229853002)(6436002)(2900100001)(55016002)(6916009)(3660700001)(39060400002)(2950100002)(5660300001)(105586002)(106356001)(33656002)(3280700002)(316002)(25786009)(54906003)(1411001)(8936002)(4326008)(8676002)(86362001)(478600001)(76176011)(68736007)(102836004)(81166006)(14454004)(97736004)(7736002)(7696005)(74316002)(53546011)(53936002)(6506007)(305945005)(3846002)(6116002)(7416002)(99286004)(59450400001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR04MB324;H:AM3PR04MB1315.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:3;A:1;LANG:en; x-microsoft-antispam-message-info: JRCzj1pGyImkKnSBs/CGLMWfIfuYJyaesNZ/HBeGaZ82u0IOI665plMRcvvFFIqy3XwqqvqY0KajQvjefVpAOg== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 151c983a-663b-4352-d488-08d55748359e X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2018 10:03:19.0094 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB324 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Best Regards! Anson Huang > -----Original Message----- > From: Dong Aisheng [mailto:dongas86@gmail.com] > Sent: 2018-01-09 5:47 PM > To: Anson Huang > Cc: Horia Geant? ; Aymen Sghaier > ; herbert@gondor.apana.org.au; > davem@davemloft.net; robh+dt@kernel.org; mark.rutland@arm.com; > shawnguo@kernel.org; kernel@pengutronix.de; Fabio Estevam > ; linux@armlinux.org.uk; > mturquette@baylibre.com; sboyd@codeaurora.org; Adriana Reus > ; stefan@agner.ch; linux-crypto@vger.kernel.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-clk@vger.kernel.org; dl-linux-imx imx@nxp.com> > Subject: Re: [PATCH V3 2/2] ARM: dts: imx7s: add snvs rtc clock > > On Tue, Jan 09, 2018 at 05:20:51PM +0800, Anson Huang wrote: > > Add i.MX7 SNVS RTC clock. > > > > Signed-off-by: Anson Huang > > --- > > changes since v2: > > improve the binding doc statement about clocks. > > Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 15 > +++++++++++++++ > > arch/arm/boot/dts/imx7s.dtsi | 2 ++ > > 2 files changed, 17 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > index 76aec8a..7329f29 100644 > > --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > @@ -415,12 +415,25 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) > RTC Node > > value type: > > Definition: LP register offset. default it is 0x34. > > > > + - clocks > > + Usage: required if SNVS LP RTC requires explicit enablement of clocks > > + Value type: > > + Definition: a clock specifier describing the clock required for > > + enabling and disabling SNVS LP RTC. > > + > > This clock seem optional. > Should we indicate it here explicitly? Will add a optional in usage. > > BTW, i thought we probably could update poweroff and key as well at the same > time since device tree changes can go separately. > Does it make sense? I think this patch set is only for RTC case since snvs-rtc driver already handle the clock. But for poweroff and powerkey, their drivers are NOT handling clocks currently, we can add them when driver ready to handle clocks. Should be in another patch set later. Anson. > > Regards > Dong Aisheng > > > + - clock-names > > + Usage: required if SNVS LP RTC requires explicit enablement of clocks > > + Value type: > > + Definition: clock name string should be "snvs-rtc". > > + > > EXAMPLE > > sec_mon_rtc_lp@1 { > > compatible = "fsl,sec-v4.0-mon-rtc-lp"; > > interrupts = <93 2>; > > regmap = <&snvs>; > > offset = <0x34>; > > + clocks = <&clks IMX7D_SNVS_CLK>; > > + clock-names = "snvs-rtc"; > > }; > > > > > ============================================================ > ========= > > @@ -543,6 +556,8 @@ FULL EXAMPLE > > regmap = <&sec_mon>; > > offset = <0x34>; > > interrupts = <93 2>; > > + clocks = <&clks IMX7D_SNVS_CLK>; > > + clock-names = "snvs-rtc"; > > }; > > > > snvs-pwrkey@020cc000 { > > diff --git a/arch/arm/boot/dts/imx7s.dtsi > > b/arch/arm/boot/dts/imx7s.dtsi index 9aa2bb9..02baf42 100644 > > --- a/arch/arm/boot/dts/imx7s.dtsi > > +++ b/arch/arm/boot/dts/imx7s.dtsi > > @@ -551,6 +551,8 @@ > > offset = <0x34>; > > interrupts = IRQ_TYPE_LEVEL_HIGH>, > > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clks IMX7D_SNVS_CLK>; > > + clock-names = "snvs-rtc"; > > }; > > > > snvs_poweroff: snvs-poweroff { > > -- > > 1.9.1 > >