Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932099AbeAIKjw (ORCPT + 1 other); Tue, 9 Jan 2018 05:39:52 -0500 Received: from mail-wm0-f54.google.com ([74.125.82.54]:46471 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754965AbeAIKju (ORCPT ); Tue, 9 Jan 2018 05:39:50 -0500 X-Google-Smtp-Source: ACJfBosV6F5DRk90WcGdNWmNpH9mlCpzfq7LKVUXVaKET9ls8vKT9WTGvXZD4slFyMZMH2SIasOcGg== Subject: Re: [PATCH v2 1/8] x86/feature: Detect the x86 IBRS feature to control Speculation To: Tim Chen , Thomas Gleixner , Andy Lutomirski , Linus Torvalds , Greg KH Cc: Dave Hansen , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , David Woodhouse , linux-kernel@vger.kernel.org References: From: Paolo Bonzini Message-ID: Date: Tue, 9 Jan 2018 11:39:46 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 06/01/2018 03:12, Tim Chen wrote: > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 34c4922..f881add 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -42,6 +42,10 @@ > #define MSR_PPIN_CTL 0x0000004e > #define MSR_PPIN 0x0000004f > > +#define MSR_IA32_SPEC_CTRL 0x00000048 > +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0) > +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0) > + > #define MSR_IA32_PERFCTR0 0x000000c1 > #define MSR_IA32_PERFCTR1 0x000000c2 > #define MSR_FSB_FREQ 0x000000cd This is the patch that I have in my KVM series: diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 03ffde6217d0..828a03425571 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -464,8 +464,15 @@ #define MSR_SMI_COUNT 0x00000034 #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_IA32_TSC_ADJUST 0x0000003b + +#define MSR_IA32_SPEC_CTRL 0x00000048 +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0) +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0) + +#define MSR_IA32_PRED_CMD 0x00000049 +#define PRED_CMD_IBPB (1UL << 0) + #define MSR_IA32_BNDCFGS 0x00000d90 - #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc #define MSR_IA32_XSS 0x00000da0 Tim, can you include it like this to avoid conflicts? Thanks, Paolo