Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754085AbeAIMD0 (ORCPT + 1 other); Tue, 9 Jan 2018 07:03:26 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:42446 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751870AbeAIMDU (ORCPT ); Tue, 9 Jan 2018 07:03:20 -0500 X-Google-Smtp-Source: ACJfBouLDUCwR3f9lRIgoarZiw/d82ObDau05LTeixX5Rl61vsLP+y6A0cC+ARX+SZnA2oaWU2+aKQ== From: Paolo Bonzini To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: rkrcmar@redhat.com, liran.alon@oracle.com, jmattson@google.com, aliguori@amazon.com, thomas.lendacky@amd.com, dwmw@amazon.co.uk, bp@alien8.de, x86@kernel.org Subject: [PATCH 2/8] x86/msr: add definitions for indirect branch predictor MSRs Date: Tue, 9 Jan 2018 13:03:04 +0100 Message-Id: <20180109120311.27565-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180109120311.27565-1-pbonzini@redhat.com> References: <20180109120311.27565-1-pbonzini@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: These MSRs are available if the CPU features SPEC_CTRL (CPUID(EAX=7,ECX=0).EDX[26]) is present. The PRED_CMD MSR is also available if the CPU feature IBPB_SUPPORT (CPUID(EAX=0x80000008).EBX[12]) is present. KVM will soon start using PRED_CMD and will make SPEC_CTRL available to guests. Reviewed-by: Liran Alon Signed-off-by: Paolo Bonzini --- arch/x86/include/asm/msr-index.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 03ffde6217d0..828a03425571 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -464,8 +464,15 @@ #define MSR_SMI_COUNT 0x00000034 #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_IA32_TSC_ADJUST 0x0000003b -#define MSR_IA32_BNDCFGS 0x00000d90 +#define MSR_IA32_SPEC_CTRL 0x00000048 +#define SPEC_CTRL_FEATURE_DISABLE_IBRS (0 << 0) +#define SPEC_CTRL_FEATURE_ENABLE_IBRS (1 << 0) + +#define MSR_IA32_PRED_CMD 0x00000049 +#define PRED_CMD_IBPB (1UL << 0) + +#define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc #define MSR_IA32_XSS 0x00000da0 -- 1.8.3.1