Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753842AbeAIOGU (ORCPT + 1 other); Tue, 9 Jan 2018 09:06:20 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35624 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751700AbeAIOGS (ORCPT ); Tue, 9 Jan 2018 09:06:18 -0500 X-Google-Smtp-Source: ACJfBov+2lGWmL2UXCXUkNSJTTIjTu3wEiRDSgXzViP7n9CdbngzbEkPwDXyxmoD+iZZjl+7xCoZlw== Subject: Re: [PATCH 0/7] KVM: x86: expose CVE-2017-5715 ("Spectre variant 2") mitigations to guest To: Thomas Gleixner Cc: LKML , kvm@vger.kernel.org, jmattson@google.com, aliguori@amazon.com, thomas.lendacky@amd.com, dwmw@amazon.co.uk, Borislav Petkov , Peter Zijlstra References: <1515434925-10250-1-git-send-email-pbonzini@redhat.com> From: Paolo Bonzini Message-ID: <76848d3f-3eda-f8cb-ab3c-366c302c757b@redhat.com> Date: Tue, 9 Jan 2018 15:06:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 09/01/2018 13:03, Thomas Gleixner wrote: > On Tue, 9 Jan 2018, Paolo Bonzini wrote: >> On 09/01/2018 11:15, Thomas Gleixner wrote: >>> On Mon, 8 Jan 2018, Paolo Bonzini wrote: >>> >>>> This series allows guests to use the MSR_IA32_SPEC_CTRL and >>>> MSR_IA32_PRED_CMD model specific registers that were added as mitigations >>>> for CVE-2017-5715. >>>> >>>> These are only the KVM specific parts of the fix. It does *not* yet >>>> include any protection for reading host memory from the guest, because >>>> that would be done in the same way as the rest of Linux. So there is no >>>> IBRS *usage* here, no retpolines, no stuffing of the return stack buffer. >>>> (KVM already includes a fix to clear all registers on vmexit, which is >>>> enough to block Google Project Zero's PoC exploit). >>>> >>>> However, I am including the changes to use IBPB (indirect branch >>>> predictor barrier) if available. That occurs only when there is a VCPU >>>> switch on a physical CPU, thus it has a small impact on performance. >>>> >>>> The patches are a bit hackish because the relevant cpufeatures have >>>> not been included yet, and because I wanted to make the patches easier >>>> to backport to distro kernels if desired, but I would still like to >>>> have them in 4.16. > > We really want to coordinate that proper with the ongoing integration of > the IB** for bare metal. Yes, this can get merged to master together with the bare-metal parts. If, as I expect, the -rc rules will be be bent a bit for IB** (and perhaps retpolines too) in 4.16, we have some time to sort it out. Thanks, Paolo > And that stuff really does not need to be hackish at all. We've spent a lot > of effort keeping all of it clean _AND_ available for 4.14 stable > consumption. Everything before 4.9 is a big fricking and incompatible mess > anyway.