Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756181AbeAIOIJ (ORCPT + 1 other); Tue, 9 Jan 2018 09:08:09 -0500 Received: from smtp.nue.novell.com ([195.135.221.5]:38299 "EHLO smtp.nue.novell.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756025AbeAIOHu (ORCPT ); Tue, 9 Jan 2018 09:07:50 -0500 Subject: Re: [PATCH v3 00/13] arm64 kpti hardening and variant 2 workarounds To: Catalin Marinas , Will Deacon Cc: lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Yousaf Kaukab References: <1515432758-26440-1-git-send-email-will.deacon@arm.com> <20180108185353.sung5ovk65au3kge@armageddon.cambridge.arm.com> From: Matthias Brugger Message-ID: <904afc66-7936-d430-f056-6aa6e64ca0a9@suse.com> Date: Tue, 9 Jan 2018 15:07:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <20180108185353.sung5ovk65au3kge@armageddon.cambridge.arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Hi Catalin, On 01/08/2018 07:53 PM, Catalin Marinas wrote: > On Mon, Jan 08, 2018 at 05:32:25PM +0000, Will Deacon wrote: >> Jayachandran C (1): >> arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs >> >> Marc Zyngier (3): >> arm64: Move post_ttbr_update_workaround to C code >> arm64: KVM: Use per-CPU vector when BP hardening is enabled >> arm64: KVM: Make PSCI_VERSION a fast path >> >> Shanker Donthineni (1): >> arm64: Implement branch predictor hardening for Falkor >> >> Will Deacon (8): >> arm64: use RET instruction for exiting the trampoline >> arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry >> arm64: Take into account ID_AA64PFR0_EL1.CSV3 >> arm64: cpufeature: Pass capability structure to ->enable callback >> drivers/firmware: Expose psci_get_version through psci_ops structure >> arm64: Add skeleton to harden the branch predictor against aliasing >> attacks >> arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 >> arm64: Implement branch predictor hardening for affected Cortex-A CPUs > > I'm queuing these into the arm64 for-next/core (after some overnight > testing). Any additional fixes should be done on top. > I see these patches are not yet pushed to: git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git Did you hit any problems in the overnight tests? Regards, Matthias