Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758641AbeAIPA6 (ORCPT + 1 other); Tue, 9 Jan 2018 10:00:58 -0500 Received: from aserp2130.oracle.com ([141.146.126.79]:41422 "EHLO aserp2130.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757138AbeAIPA4 (ORCPT ); Tue, 9 Jan 2018 10:00:56 -0500 MIME-Version: 1.0 Message-ID: Date: Tue, 9 Jan 2018 07:00:38 -0800 (PST) From: Liran Alon To: Cc: , , , , , , , Subject: Re: [PATCH 6/7] x86/svm: Set IBPB when running a different VCPU X-Mailer: Zimbra on Oracle Beehive Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Content-Disposition: inline X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8768 signatures=668652 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=808 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1801090211 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: ----- arjan@linux.intel.com wrote: > On 1/9/2018 3:41 AM, Paolo Bonzini wrote: > > The above ("IBRS simply disables the indirect branch predictor") was > my > > take-away message from private discussion with Intel. My guess is > that > > the vendors are just handwaving a spec that doesn't match what they > have > > implemented, because honestly a microcode update is unlikely to do > much > > more than an old-fashioned chicken bit. Maybe on Skylake it does > > though, since the performance characteristics of IBRS are so > different > > from previous processors. Let's ask Arjan who might have more > > information about it, and hope he actually can disclose it... > > IBRS will ensure that, when set after the ring transition, no earlier > branch prediction data is used for indirect branches while IBRS is > set Consider the following scenario: 1. L1 runs with IBRS=1 in Ring0. 2. L1 restores L2 SPEC_CTRL and enters into L2. 3. L1 VMRUN exits into L0 which backups L1 SPEC_CTRL and enters L2 (using same VMCB). 4. L2 populates BTB/BHB with values and cause a hypercall which #VMExit into L0. 5. L0 backups L2 SPEC_CTRL and writes IBRS=1. 6. L0 restores L1 SPEC_CTRL and enters L1. 7. L1 backups L2 SPEC_CTRL and writes IBRS=1. Just to make sure I understand: You state that L2 BTB/BHB won't be used by L1 because L1 have set IBRS=1 in step (7). And that is even though L1 & L2 could both be running in SVM guest-mode & Ring0 from physical CPU perspective. Therefore, having the same prediction-mode. So basically you are saying that IBRS don't make sure to avoid using BTB/BHB from lower prediction-modes but instead just make sure to avoid usage of all BTB/BHB while IBRS is set. Did I understand everything correctly? Thanks, -Liran > > (this is a english summary of two pages of technical spec so it lacks > the language lawyer precision) > > because of this promise, the implementation tends to be impactful > and it is very strongly recommended that retpoline is used instead of > IBRS. > (with all the caveats already on lkml) > > the IBPB is different, this is a covenient thing for switching between > VM guests etc