Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758910AbeAIPfr (ORCPT + 1 other); Tue, 9 Jan 2018 10:35:47 -0500 Received: from aserp2120.oracle.com ([141.146.126.78]:37298 "EHLO aserp2120.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758850AbeAIPfo (ORCPT ); Tue, 9 Jan 2018 10:35:44 -0500 MIME-Version: 1.0 Message-ID: <2779f941-9011-4dd1-8ef0-6b035fbf0e2f@default> Date: Tue, 9 Jan 2018 07:33:27 -0800 (PST) From: Liran Alon To: Cc: , , , , , , , Subject: Re: [PATCH 6/7] x86/svm: Set IBPB when running a different VCPU X-Mailer: Zimbra on Oracle Beehive Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Content-Disposition: inline X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8768 signatures=668652 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=973 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1801090219 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: ----- arjan@linux.intel.com wrote: > On 1/9/2018 7:00 AM, Liran Alon wrote: > > > > ----- arjan@linux.intel.com wrote: > > > >> On 1/9/2018 3:41 AM, Paolo Bonzini wrote: > >>> The above ("IBRS simply disables the indirect branch predictor") > was > >> my > >>> take-away message from private discussion with Intel. My guess > is > >> that > >>> the vendors are just handwaving a spec that doesn't match what > they > >> have > >>> implemented, because honestly a microcode update is unlikely to > do > >> much > >>> more than an old-fashioned chicken bit. Maybe on Skylake it does > >>> though, since the performance characteristics of IBRS are so > >> different > >>> from previous processors. Let's ask Arjan who might have more > >>> information about it, and hope he actually can disclose it... > >> > >> IBRS will ensure that, when set after the ring transition, no > earlier > >> branch prediction data is used for indirect branches while IBRS is > >> set > > > > Consider the following scenario: > > 1. L1 runs with IBRS=1 in Ring0. > > 2. L1 restores L2 SPEC_CTRL and enters into L2. > > 3. L1 VMRUN exits into L0 which backups L1 SPEC_CTRL and enters L2 > (using same VMCB). > > 4. L2 populates BTB/BHB with values and cause a hypercall which > #VMExit into L0. > > 5. L0 backups L2 SPEC_CTRL and writes IBRS=1. > > 6. L0 restores L1 SPEC_CTRL and enters L1. > > 7. L1 backups L2 SPEC_CTRL and writes IBRS=1. > > > > I'm sorry I'm not familiar with your L0/L1/L2 terminology > (maybe it's before coffee has had time to permeate the brain) These are standard terminology for guest levels: L0 == hypervisor that runs on bare-metal L1 == hypervisor that runs as L0 guest. L2 == software that runs as L1 guest. (We are talking about nested virtualization here) -Liran