Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934307AbeAIQRu (ORCPT + 1 other); Tue, 9 Jan 2018 11:17:50 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:46104 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933559AbeAIQRr (ORCPT ); Tue, 9 Jan 2018 11:17:47 -0500 X-Google-Smtp-Source: ACJfBouIlgmmNxRNxxRhv1rNInojY7zAZVVTXklBYRZTsmBA4Ncfzh7rqt/0IhZbHsi+XzctbGqJ4A== Subject: Re: [PATCH 6/7] x86/svm: Set IBPB when running a different VCPU To: Arjan van de Ven , Liran Alon Cc: jmattson@google.com, dwmw@amazon.co.uk, bp@alien8.de, aliguori@amazon.com, thomas.lendacky@amd.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org References: From: Paolo Bonzini Message-ID: <74e86dd8-804e-c9f2-098f-773283ac7065@redhat.com> Date: Tue, 9 Jan 2018 17:17:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 09/01/2018 16:19, Arjan van de Ven wrote: > On 1/9/2018 7:00 AM, Liran Alon wrote: >> >> ----- arjan@linux.intel.com wrote: >> >>> On 1/9/2018 3:41 AM, Paolo Bonzini wrote: >>>> The above ("IBRS simply disables the indirect branch predictor") was my >>>> take-away message from private discussion with Intel.  My guess is that >>>> the vendors are just handwaving a spec that doesn't match what they have >>>> implemented, because honestly a microcode update is unlikely to do much >>>> more than an old-fashioned chicken bit.  Maybe on Skylake it does >>>> though, since the performance characteristics of IBRS are so different >>>> from previous processors.  Let's ask Arjan who might have more >>>> information about it, and hope he actually can disclose it... >>> >>> IBRS will ensure that, when set after the ring transition, no earlier >>> branch prediction data is used for indirect branches while IBRS is >>> set Let me ask you my questions, which are independent of L0/L1/L2 terminology. 1) Is vmentry/vmexit considered a ring transition, even if the guest is running in ring 0? If IBRS=1 in the guest and the host is using IBRS, the host will not do a wrmsr on exit. Is this safe for the host kernel? 2) How will the future processors work where IBRS should always be =1? Will they still need IBPB? If I get a vmexit from a guest with IBRS=1, and do a vmentry to the same VMCS *but with a different VPID*, will the code running after the vmentry share BTB entries with code running before the vmexit? Thanks, Paolo