Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935387AbeAITJx (ORCPT + 1 other); Tue, 9 Jan 2018 14:09:53 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:59786 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935233AbeAITFB (ORCPT ); Tue, 9 Jan 2018 14:05:01 -0500 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, kristina.martsenko@arm.com, peter.maydell@linaro.org, suzuki.poulose@arm.com, pbonzini@redhat.com, rkrcmar@redhat.com, will.deacon@arm.com, ard.biesheuvel@linaro.org, mark.rutland@arm.com, catalin.marinas@arm.com Subject: [PATCH v1 05/16] arm64: Helper for parange to PASize Date: Tue, 9 Jan 2018 19:04:00 +0000 Message-Id: <20180109190414.4017-6-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180109190414.4017-1-suzuki.poulose@arm.com> References: <20180109190414.4017-1-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical size shift. Limit the size to the maximum supported by the kernel. Cc: Mark Rutland Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Signed-off-by: Suzuki K Poulose --- arch/arm64/include/asm/cpufeature.h | 16 ++++++++++++++++ arch/arm64/kvm/hyp/s2-setup.c | 28 +++++----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index ac67cfc2585a..0564e14616eb 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -304,6 +304,22 @@ static inline u64 read_zcr_features(void) return zcr; } +static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) +{ + switch (parange) { + case 0: return 32; + case 1: return 36; + case 2: return 40; + case 3: return 42; + case 4: return 44; + + default: + case 5: return 48; +#ifdef CONFIG_ARM64_PA_BITS_52 + case 6: return 52; +#endif + } +} #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c index 603e1ee83e89..b1129c83c531 100644 --- a/arch/arm64/kvm/hyp/s2-setup.c +++ b/arch/arm64/kvm/hyp/s2-setup.c @@ -19,11 +19,13 @@ #include #include #include +#include u32 __hyp_text __init_stage2_translation(void) { u64 val = VTCR_EL2_FLAGS; u64 parange; + u32 phys_shift; u64 tmp; /* @@ -37,27 +39,7 @@ u32 __hyp_text __init_stage2_translation(void) val |= parange << 16; /* Compute the actual PARange... */ - switch (parange) { - case 0: - parange = 32; - break; - case 1: - parange = 36; - break; - case 2: - parange = 40; - break; - case 3: - parange = 42; - break; - case 4: - parange = 44; - break; - case 5: - default: - parange = 48; - break; - } + phys_shift = id_aa64mmfr0_parange_to_phys_shift(parange); /* * ... and clamp it to 40 bits, unless we have some braindead @@ -65,7 +47,7 @@ u32 __hyp_text __init_stage2_translation(void) * return that value for the rest of the kernel to decide what * to do. */ - val |= 64 - (parange > 40 ? 40 : parange); + val |= 64 - (phys_shift > 40 ? 40 : phys_shift); /* * Check the availability of Hardware Access Flag / Dirty Bit @@ -86,5 +68,5 @@ u32 __hyp_text __init_stage2_translation(void) write_sysreg(val, vtcr_el2); - return parange; + return phys_shift; } -- 2.13.6