Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934079AbeAJFDd (ORCPT + 1 other); Wed, 10 Jan 2018 00:03:33 -0500 Received: from mail-pg0-f53.google.com ([74.125.83.53]:45799 "EHLO mail-pg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751325AbeAJFDb (ORCPT ); Wed, 10 Jan 2018 00:03:31 -0500 X-Google-Smtp-Source: ACJfBovvCo5J9+KiKxGjijTlizhen+IH6Ok028liyi+sefWXMF5UuVFzpuVb8YwP7XICn3Sic6wmAg== Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 10.3 \(3273\)) Subject: Re: [PATCH 3/8] kvm: vmx: pass MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD down to the guest From: Nadav Amit In-Reply-To: <834e9b46-5d59-a81e-8cda-5f576964e1cb@redhat.com> Date: Tue, 9 Jan 2018 21:03:27 -0800 Cc: Liran Alon , jmattson@google.com, x86@kernel.org, dwmw@amazon.co.uk, bp@alien8.de, aliguori@amazon.com, thomas.lendacky@amd.com, rkrcmar@redhat.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Transfer-Encoding: 8BIT Message-Id: References: <222d0a6b-820f-4d7c-a616-ac89f77c3c09@default> <834e9b46-5d59-a81e-8cda-5f576964e1cb@redhat.com> To: Paolo Bonzini X-Mailer: Apple Mail (2.3273) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Paolo Bonzini wrote: > On 09/01/2018 17:48, Liran Alon wrote: >>>> + if (have_spec_ctrl) { >>>> + rdmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl); >>>> + if (vmx->spec_ctrl != 0) >>>> + wrmsrl(MSR_IA32_SPEC_CTRL, 0); >> >> As I said also on the AMD patch, I think this is a bug. >> Intel specify that we should set IBRS bit even if it was already set on every #VMExit. > > That's correct (though I'd like to understand _why_---I'm not inclined > to blindly trust a spec), but for now it's saving a wrmsr of 0. That is > quite obviously okay, and will be also okay after the bare-metal IBRS > patches. > > Of course the code will become something like > > if (using_ibrs || vmx->spec_ctrl != 0) > wrmsrl(MSR_IA32_SPEC_CTRL, host_ibrs); > > optimizing the case where the host is using retpolines. Excuse my ignorance: Can you point me to the specifications that mention “we should set IBRS bit even if it was already set on every #VMExit” ? Thanks, Nadav