Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965493AbeAJPNf (ORCPT + 1 other); Wed, 10 Jan 2018 10:13:35 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41686 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964976AbeAJPNe (ORCPT ); Wed, 10 Jan 2018 10:13:34 -0500 Date: Wed, 10 Jan 2018 16:13:17 +0100 From: Andrea Arcangeli To: Dave Hansen Cc: Thomas Gleixner , David Woodhouse , Jiri Kosina , "asit.k.mallick" , "Van De Ven, Arjan" , Peter Zijlstra , LKML , Linus Torvalds , x86@kernel.org, Borislav Petkov , Tim Chen , Andi Kleen , Greg KH , Andy Lutomirski Subject: Re: [patch RFC 5/5] x86/speculation: Add basic speculation control code Message-ID: <20180110151317.GI9417@redhat.com> References: <1515586174.22302.126.camel@infradead.org> <20180110121755.GD9706@redhat.com> <1515587384.22302.132.camel@infradead.org> <20180110124119.GG9706@redhat.com> <20180110125710.GH9706@redhat.com> <1515589641.22302.145.camel@infradead.org> <20180110141047.GD9417@redhat.com> <1610a587-fe9e-28bd-dcd1-b9ec940c07ef@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1610a587-fe9e-28bd-dcd1-b9ec940c07ef@intel.com> User-Agent: Mutt/1.9.2 (2017-12-15) X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Wed, 10 Jan 2018 15:13:34 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Wed, Jan 10, 2018 at 06:59:54AM -0800, Dave Hansen wrote: > On 01/10/2018 06:10 AM, Andrea Arcangeli wrote: > > Tim and Dave please comment too, Tim you originally wrote that code > > that leaves IBRS always on and never toggles it in the kernel entry > > point so you must know full well if Arjan is correct that you must > > toggle IBRS every time you enter kernel and in turn ibrs_enabled 2 > > isn't valid mode. > > Hi Andrea, > > The "writing IBRS=1 acts as a barrier when it is already IBRS=1" > behavior is something which I misunderstood in the past. Thanks, Arjan, > for clearing it up. "writing IBRS=1 acts as a barrier when it is already IBRS=1" would have been much clearer wording frankly. IBPB is IBP "Barrier", but also IBRS is a barrier, no problem :). So we'll add a dummy IBRS write to SPEC_CTRL in kernel entry and vmexit so that it is compliant with all released microcodes that may require it, also when ibrs_enabled is 2. Can you confirm? Can you also tell if IBRS must be written as a barrier to SPEC_CTRL in return to userland (kernel exit) when ibrs_enabled 2? Generally we wouldn't run a barrier there with ibrs_enabled 2, but absolutely nothing is intuitive here so I need to ask explicitly.