Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965795AbeAJPvK (ORCPT + 1 other); Wed, 10 Jan 2018 10:51:10 -0500 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:51226 "EHLO smtp-fw-9102.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965275AbeAJPvH (ORCPT ); Wed, 10 Jan 2018 10:51:07 -0500 X-Amazon-filename: smime.p7s X-IronPort-AV: E=Sophos;i="5.46,340,1511827200"; d="p7s'?scan'208";a="585411261" Message-ID: <1515599333.22302.195.camel@amazon.co.uk> Subject: Re: [PATCH 3/8] kvm: vmx: pass MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD down to the guest To: Konrad Rzeszutek Wilk , Paolo Bonzini CC: Arjan van de Ven , Nadav Amit , Liran Alon , , , , , , , , In-Reply-To: <20180110154138.GE29272@char.us.oracle.com> References: <222d0a6b-820f-4d7c-a616-ac89f77c3c09@default> <834e9b46-5d59-a81e-8cda-5f576964e1cb@redhat.com> <9360a280-228d-26d9-5561-6688aa67881c@linux.intel.com> <91d41f66-d744-e8b0-89f0-a167d3a3918c@redhat.com> <20180110154138.GE29272@char.us.oracle.com> Face: iVBORw0KGgoAAAANSUhEUgAAADAAAAAwBAMAAAClLOS0AAAAG1BMVEUHBwcUFBQpKSlGRkZhYWF9fX2Xl5eysrLMzMxFF+rXAAACaElEQVQ4y21UQXbbIBQE9wJALmAg6ToWON22FrhZthHgbvssUPathC7QWMful2JHSmtWwGg+zPxBCE0DU4QoJQgRgsg4w2gJjBNE8PjFBZgnQMBs+uZ1NQNQjZO3BV4AGDFC0f+l4DBG0VUAM4yv7SO8IgRdHXQ+A78HKL5OAeCfNQV5cHX8DsBUyIJKtYbt98BKaGNCKjfgFVkqYVLbkHKsRsbSCSa0T6npIqLrpRBgQKHUpQmgs9eEKaiUcooE8WWfCGVnBiUcn1uF2XhbfmN9apKnmMP2K4kizKkQWxuaVNOpU2cACIyxO1Po8ETHcXEDMVnozcejkAYA9iaD4pU0ZvNQ8VurNnTuFAYVtuIPUZW25PjDIjQAlGyffIiRQxoWAZBmJ0LTdW2Nyc0iP3DqRhxizvGJkBWZmyFVyZkddWzmBoIBVMpCCJ1CFzl98xav4VJKSSD45KbUT75ixikTphDSRh8+Uz7JLgUTAgAFwzqzjxc/nDY7WUApqY0OMdTwCKZSXplSKkgIRCHElCp8ZnhnKqXuwcNbk1L0VXE+I9alUXoHlLHl3mv7/dWQlJwtjREC7mu9L/U2jQyMUuO2EDS4q9Kl2ddm232bxIE5pjJuVwiljNn/Cfv25/T0cu5cZbwHGVq7h/zp0B4n3S99V/utD+Uo8BiGx9xCsOAV5z7/tjo4Z4z1Lvb90KZ7eFOoOeXOukqF2seo234YYuaQPpRP+cVZU5adT1Edun5Iz3z8fTz3+eSDh0Ip1c7zx1MaijGzTd/3MbRuBHz8cvcVgCMBRpOHvgu59WDhoat+nIZm+LWm9C/aaaGq5DCP9QAAAABJRU5ErkJggg== Organization: Amazon Content-Type: multipart/signed; micalg=sha-256; protocol="application/x-pkcs7-signature"; boundary="=-nnEUN3z5xAk6inyqlyHX" Date: Wed, 10 Jan 2018 15:48:53 +0000 X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 MIME-Version: 1.0 From: "Woodhouse, David" X-Evolution-Source: 1481217574.17989.4@uc8d3ff76b9bc5848a9cc Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: --=-nnEUN3z5xAk6inyqlyHX Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2018-01-10 at 10:41 -0500, Konrad Rzeszutek Wilk wrote: > On Wed, Jan 10, 2018 at 03:28:43PM +0100, Paolo Bonzini wrote: > > On 10/01/2018 15:06, Arjan van de Ven wrote: > > > On 1/10/2018 5:20 AM, Paolo Bonzini wrote: > > >> * a simple specification that does "IBRS=3D1 blocks indirect > branch > > >> prediction altogether" would actually satisfy the specification > just as > > >> well, and it would be nice to know if that's what the processor > actually > > >> does. > > >=C2=A0 > > > it doesn't exactly, not for all. > > >=C2=A0 > > > so you really do need to write ibrs again. > >=C2=A0 > > Okay, so "always set IBRS=3D1" does *not* protect against variant 2.=C2= =A0 > Thanks, >=20 > And what is the point of this "always set IBRS=3D1" then? Are there > some other things lurking in the shadows? Yes. *FUTURE* CPUs will have a mode where you can just set IBRS and leave it set for ever and not worry about any of this, and the performance won't even suck. Quite why it's still an option you have to set in an MSR, and not just a feature bit that they advertise and do it unconditionally, I have no idea. But apparently that's the plan. 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