Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966081AbeAJRPB (ORCPT + 1 other); Wed, 10 Jan 2018 12:15:01 -0500 Received: from mail-io0-f193.google.com ([209.85.223.193]:43531 "EHLO mail-io0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934222AbeAJRO7 (ORCPT ); Wed, 10 Jan 2018 12:14:59 -0500 X-Google-Smtp-Source: ACJfBovnuXrpF0KW37GgYuT5bJAtt0AE4TppWR6KIhrvxJz+Df3ze5CCmfA2yZjwqSde4a0QPOfg88o7cpm4nIeta3A= MIME-Version: 1.0 In-Reply-To: <65578664-e3ec-f894-4e94-ff9fe6d7d6b3@redhat.com> References: <65578664-e3ec-f894-4e94-ff9fe6d7d6b3@redhat.com> From: Jim Mattson Date: Wed, 10 Jan 2018 09:14:57 -0800 Message-ID: Subject: Re: [PATCH 3/8] kvm: vmx: pass MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD down to the guest To: Paolo Bonzini Cc: Liran Alon , dwmw@amazon.co.uk, Konrad Rzeszutek Wilk , "the arch/x86 maintainers" , bp@alien8.de, Nadav Amit , Tom Lendacky , aliguori@amazon.com, Arjan van de Ven , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , LKML , kvm list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Wed, Jan 10, 2018 at 8:27 AM, Paolo Bonzini wrote: > I can answer (2) only. > > On 10/01/2018 17:19, Liran Alon wrote: >> (2) On VMExit, Intel recommends to always save guest SPEC_CTRL value, >> set IBRS to 1 (even if it is already set by guest) and stuff RSB. What >> exactly does this write of 1 to IBRS do? >> * a) Does it keep all currently existing BTB/BHB entries created by >> less-privileged prediction-mode and marks them as were created in >> less-privileged prediction-mode such that they won't be used in current >> prediction-mode? >> * b) Or does it, as Paolo has mentioned multiple times, disables the >> branch predictor to never consult the BTB/BHB at all as long as IBRS=1? >> If (b) is true, why is setting IBRS=1 better than just issue an IBPB that clears all entries? At least in that case the > host kernel could still benefict branch prediction performance boost. > > Arjan said (b) is not true on all processor generations. But even if it > were true, setting IBRS=1 is much, much faster than IBPB. > >> If (a) is true, does "IBRS ALL THE TIME" usage is basically a CPU >> change to just create all BTB/BHB entries to be tagged with >> prediction-mode at creation-time and that tag to be compared to current >> prediction-mode when CPU attempts to use BTB/BHB? > > I hope so, and I hope said prediction mode includes PCID/VPID too. Branch prediction entries should probably be tagged with PCID, VPID, EP4TA, and thread ID...the same things used to tag TLB contexts. > While I agree with David that "we have other things to work on for now > before we support hypothetical future hardware", I'd like to make sure > that Intel gets it right... > > Paolo