Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752651AbeAJWnu (ORCPT + 1 other); Wed, 10 Jan 2018 17:43:50 -0500 Received: from 9pmail.ess.barracuda.com ([64.235.150.224]:60786 "EHLO 9pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751911AbeAJWnt (ORCPT ); Wed, 10 Jan 2018 17:43:49 -0500 Date: Wed, 10 Jan 2018 22:42:34 +0000 From: James Hogan To: Paul Cercueil CC: Ralf Baechle , Maarten ter Huurne , Paul Burton , , Subject: Re: [PATCH v6 11/15] MIPS: ingenic: Initial JZ4770 support Message-ID: <20180110224233.GV27409@jhogan-linux.mipstec.com> References: <20180102150848.11314-1-paul@crapouillou.net> <20180105182513.16248-1-paul@crapouillou.net> <20180105182513.16248-12-paul@crapouillou.net> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bn6XL8m8Y51x7rzV" Content-Disposition: inline In-Reply-To: <20180105182513.16248-12-paul@crapouillou.net> User-Agent: Mutt/1.7.2 (2016-11-26) X-Originating-IP: [192.168.154.110] X-BESS-ID: 1515624208-298555-2578-1082-6 X-BESS-VER: 2017.17-r1801091856 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.188374 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: --bn6XL8m8Y51x7rzV Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jan 05, 2018 at 07:25:09PM +0100, Paul Cercueil wrote: > Provide just enough bits (clocks, clocksource, uart) to allow a kernel > to boot on the JZ4770 SoC to a initramfs userspace. >=20 > Signed-off-by: Paul Cercueil > Reviewed-by: PrasannaKumar Muralidharan > --- > arch/mips/boot/dts/ingenic/jz4770.dtsi | 212 +++++++++++++++++++++++++++= ++++++ > arch/mips/jz4740/Kconfig | 6 + > arch/mips/jz4740/time.c | 2 +- > 3 files changed, 219 insertions(+), 1 deletion(-) > create mode 100644 arch/mips/boot/dts/ingenic/jz4770.dtsi We should probably have a MAINTAINERS entry including this file. Same goes for the GC0 files added in the last patch. Cheers James >=20 > v2: No change > v3: No change > v4: No change > v5: Use SPDX license identifier > v6: No change >=20 > diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/= ingenic/jz4770.dtsi > new file mode 100644 > index 000000000000..7c2804f3f5f1 > --- /dev/null > +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi > @@ -0,0 +1,212 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +#include > + > +/ { > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + compatible =3D "ingenic,jz4770"; > + > + cpuintc: interrupt-controller { > + #address-cells =3D <0>; > + #interrupt-cells =3D <1>; > + interrupt-controller; > + compatible =3D "mti,cpu-interrupt-controller"; > + }; > + > + intc: interrupt-controller@10001000 { > + compatible =3D "ingenic,jz4770-intc"; > + reg =3D <0x10001000 0x40>; > + > + interrupt-controller; > + #interrupt-cells =3D <1>; > + > + interrupt-parent =3D <&cpuintc>; > + interrupts =3D <2>; > + }; > + > + ext: ext { > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + }; > + > + osc32k: osc32k { > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + clock-frequency =3D <32768>; > + }; > + > + cgu: jz4770-cgu@10000000 { > + compatible =3D "ingenic,jz4770-cgu"; > + reg =3D <0x10000000 0x100>; > + > + clocks =3D <&ext>, <&osc32k>; > + clock-names =3D "ext", "osc32k"; > + > + #clock-cells =3D <1>; > + }; > + > + pinctrl: pin-controller@10010000 { > + compatible =3D "ingenic,jz4770-pinctrl"; > + reg =3D <0x10010000 0x600>; > + > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + gpa: gpio@0 { > + compatible =3D "ingenic,jz4770-gpio"; > + reg =3D <0>; > + > + gpio-controller; > + gpio-ranges =3D <&pinctrl 0 0 32>; > + #gpio-cells =3D <2>; > + > + interrupt-controller; > + #interrupt-cells =3D <2>; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <17>; > + }; > + > + gpb: gpio@1 { > + compatible =3D "ingenic,jz4770-gpio"; > + reg =3D <1>; > + > + gpio-controller; > + gpio-ranges =3D <&pinctrl 0 32 32>; > + #gpio-cells =3D <2>; > + > + interrupt-controller; > + #interrupt-cells =3D <2>; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <16>; > + }; > + > + gpc: gpio@2 { > + compatible =3D "ingenic,jz4770-gpio"; > + reg =3D <2>; > + > + gpio-controller; > + gpio-ranges =3D <&pinctrl 0 64 32>; > + #gpio-cells =3D <2>; > + > + interrupt-controller; > + #interrupt-cells =3D <2>; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <15>; > + }; > + > + gpd: gpio@3 { > + compatible =3D "ingenic,jz4770-gpio"; > + reg =3D <3>; > + > + gpio-controller; > + gpio-ranges =3D <&pinctrl 0 96 32>; > + #gpio-cells =3D <2>; > + > + interrupt-controller; > + #interrupt-cells =3D <2>; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <14>; > + }; > + > + gpe: gpio@4 { > + compatible =3D "ingenic,jz4770-gpio"; > + reg =3D <4>; > + > + gpio-controller; > + gpio-ranges =3D <&pinctrl 0 128 32>; > + #gpio-cells =3D <2>; > + > + interrupt-controller; > + #interrupt-cells =3D <2>; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <13>; > + }; > + > + gpf: gpio@5 { > + compatible =3D "ingenic,jz4770-gpio"; > + reg =3D <5>; > + > + gpio-controller; > + gpio-ranges =3D <&pinctrl 0 160 32>; > + #gpio-cells =3D <2>; > + > + interrupt-controller; > + #interrupt-cells =3D <2>; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <12>; > + }; > + }; > + > + uart0: serial@10030000 { > + compatible =3D "ingenic,jz4770-uart"; > + reg =3D <0x10030000 0x100>; > + > + clocks =3D <&ext>, <&cgu JZ4770_CLK_UART0>; > + clock-names =3D "baud", "module"; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <5>; > + > + status =3D "disabled"; > + }; > + > + uart1: serial@10031000 { > + compatible =3D "ingenic,jz4770-uart"; > + reg =3D <0x10031000 0x100>; > + > + clocks =3D <&ext>, <&cgu JZ4770_CLK_UART1>; > + clock-names =3D "baud", "module"; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <4>; > + > + status =3D "disabled"; > + }; > + > + uart2: serial@10032000 { > + compatible =3D "ingenic,jz4770-uart"; > + reg =3D <0x10032000 0x100>; > + > + clocks =3D <&ext>, <&cgu JZ4770_CLK_UART2>; > + clock-names =3D "baud", "module"; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <3>; > + > + status =3D "disabled"; > + }; > + > + uart3: serial@10033000 { > + compatible =3D "ingenic,jz4770-uart"; > + reg =3D <0x10033000 0x100>; > + > + clocks =3D <&ext>, <&cgu JZ4770_CLK_UART3>; > + clock-names =3D "baud", "module"; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <2>; > + > + status =3D "disabled"; > + }; > + > + uhc: uhc@13430000 { > + compatible =3D "generic-ohci"; > + reg =3D <0x13430000 0x1000>; > + > + clocks =3D <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>; > + assigned-clocks =3D <&cgu JZ4770_CLK_UHC>; > + assigned-clock-rates =3D <48000000>; > + > + interrupt-parent =3D <&intc>; > + interrupts =3D <20>; > + > + status =3D "disabled"; > + }; > +}; > diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig > index 643af2012e14..29a9361a2b77 100644 > --- a/arch/mips/jz4740/Kconfig > +++ b/arch/mips/jz4740/Kconfig > @@ -18,6 +18,12 @@ config MACH_JZ4740 > bool > select SYS_HAS_CPU_MIPS32_R1 > =20 > +config MACH_JZ4770 > + bool > + select MIPS_CPU_SCACHE > + select SYS_HAS_CPU_MIPS32_R2 > + select SYS_SUPPORTS_HIGHMEM > + > config MACH_JZ4780 > bool > select MIPS_CPU_SCACHE > diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c > index bb1ad5119da4..2ca9160f642a 100644 > --- a/arch/mips/jz4740/time.c > +++ b/arch/mips/jz4740/time.c > @@ -113,7 +113,7 @@ static struct clock_event_device jz4740_clockevent = =3D { > #ifdef CONFIG_MACH_JZ4740 > .irq =3D JZ4740_IRQ_TCU0, > #endif > -#ifdef CONFIG_MACH_JZ4780 > +#if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780) > .irq =3D JZ4780_IRQ_TCU2, > #endif > }; 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