Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753489AbeAKB7V (ORCPT + 1 other); Wed, 10 Jan 2018 20:59:21 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:55425 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753278AbeAKB7Q (ORCPT ); Wed, 10 Jan 2018 20:59:16 -0500 From: Chris Packham To: gregory.clement@free-electrons.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, andrew@lunn.ch Cc: jason@lakedaemon.net, sebastian.hesselbarth@gmail.com, linux@armlinux.org.uk, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2 0/3] ARM: mvebu: dts: updates to enable EDAC Date: Thu, 11 Jan 2018 14:59:00 +1300 Message-Id: <20180111015903.11322-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.15.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: I've split this off from my earlier series[1] this is just the dts changes that will enable support for the EDAC series when it lands. The Armada 38x as well as the 98dx3236 and similar switch chips with integrated CPUs use the same SDRAM controller block as the Armada XP. The key difference is the width of the DDR interface. [1] - https://marc.info/?l=linux-kernel&m=151545124505964&w=2 Changes in v2: - update commit message - add labels to dts Chris Packham (3): ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg ARM: dts: armada-xp: add label to sdram-controller node ARM: dts: mvebu: add sdram controller node to Armada-38x arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 2 +- arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++ arch/arm/boot/dts/armada-xp.dtsi | 2 +- 4 files changed, 12 insertions(+), 2 deletions(-) -- 2.15.1