Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932499AbeAKGsq (ORCPT + 1 other); Thu, 11 Jan 2018 01:48:46 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:34785 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932297AbeAKGrY (ORCPT ); Thu, 11 Jan 2018 01:47:24 -0500 X-Google-Smtp-Source: ACJfBot9vuuVN38Ex2fnlfvF6FyJYdLDMSZBfQpKtjtKut118hFhS0f8LTuZ1PIV80tWpaR4cGkzPA== From: "Ji-Ze Hong (Peter Hong)" X-Google-Original-From: "Ji-Ze Hong (Peter Hong)" To: johan@kernel.org Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, peter_hong@fintek.com.tw, "Ji-Ze Hong (Peter Hong)" Subject: [PATCH V3 2/6] usb: serial: f81534: add auto RTS direction support Date: Thu, 11 Jan 2018 14:47:16 +0800 Message-Id: <1515653240-5420-2-git-send-email-hpeter+linux_kernel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515653240-5420-1-git-send-email-hpeter+linux_kernel@gmail.com> References: <1515653240-5420-1-git-send-email-hpeter+linux_kernel@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The F81532/534 had auto RTS direction support for RS485 mode. We'll read it from internal Flash with address 0x2f01~0x2f04 for 4 ports. There are 4 conditions below: 0: F81534_PORT_CONF_RS232. 1: F81534_PORT_CONF_RS485. 2: value error, default to F81534_PORT_CONF_RS232. 3: F81534_PORT_CONF_RS485_INVERT. F81532/534 Clock register (offset +08h) Bit0: UART Enable (always on) Bit2-1: Clock source selector 00: 1.846MHz. 01: 18.46MHz. 10: 24MHz. 11: 14.77MHz. Bit4: Auto direction(RTS) control (RTS pin Low when TX) Bit5: Invert direction(RTS) when Bit4 enabled (RTS pin high when TX) Signed-off-by: Ji-Ze Hong (Peter Hong) --- V3: 1: change some BIT() operation to GENMASK(). 2: change some dev_info() to dev_dbg(). V2: 1: Read the configure data from flash and save it to shadow clock register. drivers/usb/serial/f81534.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/usb/serial/f81534.c b/drivers/usb/serial/f81534.c index 1563d3f34381..2201be577dd3 100644 --- a/drivers/usb/serial/f81534.c +++ b/drivers/usb/serial/f81534.c @@ -98,11 +98,16 @@ #define F81534_DEFAULT_BAUD_RATE 9600 +#define F81534_PORT_CONF_RS232 0 +#define F81534_PORT_CONF_RS485 BIT(0) +#define F81534_PORT_CONF_RS485_INVERT GENMASK(1, 0) #define F81534_PORT_CONF_DISABLE_PORT BIT(3) #define F81534_PORT_CONF_NOT_EXIST_PORT BIT(7) #define F81534_PORT_UNAVAILABLE \ (F81534_PORT_CONF_DISABLE_PORT | F81534_PORT_CONF_NOT_EXIST_PORT) +#define F81534_UART_MODE_MASK GENMASK(1, 0) + #define F81534_1X_RXTRIGGER 0xc3 #define F81534_8X_RXTRIGGER 0xcf @@ -115,6 +120,8 @@ * 01: 18.46MHz. * 10: 24MHz. * 11: 14.77MHz. + * Bit4: Auto direction(RTS) control (RTS pin Low when TX) + * Bit5: Invert direction(RTS) when Bit4 enabled (RTS pin high when TX) */ #define F81534_UART_EN BIT(0) @@ -123,6 +130,8 @@ #define F81534_CLK_24_MHZ BIT(2) #define F81534_CLK_14_77_MHZ GENMASK(2, 1) #define F81534_CLK_MASK GENMASK(2, 1) +#define F81534_CLK_RS485_MODE BIT(4) +#define F81534_CLK_RS485_INVERT BIT(5) static const struct usb_device_id f81534_id_table[] = { { USB_DEVICE(FINTEK_VENDOR_ID_1, FINTEK_DEVICE_ID) }, @@ -1274,9 +1283,12 @@ static void f81534_lsr_worker(struct work_struct *work) static int f81534_port_probe(struct usb_serial_port *port) { + struct f81534_serial_private *serial_priv; struct f81534_port_private *port_priv; int ret; + u8 value; + serial_priv = usb_get_serial_data(port->serial); port_priv = devm_kzalloc(&port->dev, sizeof(*port_priv), GFP_KERNEL); if (!port_priv) return -ENOMEM; @@ -1309,6 +1321,24 @@ static int f81534_port_probe(struct usb_serial_port *port) if (ret) return ret; + value = serial_priv->conf_data[port_priv->phy_num]; + switch (value & F81534_UART_MODE_MASK) { + case F81534_PORT_CONF_RS485_INVERT: + port_priv->shadow_clk |= F81534_CLK_RS485_MODE | + F81534_CLK_RS485_INVERT; + dev_dbg(&port->dev, "RS485 invert mode.\n"); + break; + case F81534_PORT_CONF_RS485: + port_priv->shadow_clk |= F81534_CLK_RS485_MODE; + dev_dbg(&port->dev, "RS485 mode.\n"); + break; + + default: + case F81534_PORT_CONF_RS232: + dev_dbg(&port->dev, "RS232 mode.\n"); + break; + } + return 0; } -- 2.7.4