Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933380AbeAKKdV (ORCPT + 1 other); Thu, 11 Jan 2018 05:33:21 -0500 Received: from mail-lf0-f66.google.com ([209.85.215.66]:46394 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933058AbeAKKdT (ORCPT ); Thu, 11 Jan 2018 05:33:19 -0500 X-Google-Smtp-Source: ACJfBovorl0Bh7CN2l14+his8FCneVoY35lE5SuEN8q6/mte2jBOb1sc7D+tqp+qEfoFo594QGRLaQ== Subject: Re: [PATCH 6/8] kvm: svm: pass MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD down to guest To: Tom Lendacky , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: rkrcmar@redhat.com, liran.alon@oracle.com, jmattson@google.com, aliguori@amazon.com, dwmw@amazon.co.uk, bp@alien8.de, x86@kernel.org References: <20180109120311.27565-1-pbonzini@redhat.com> <20180109120311.27565-7-pbonzini@redhat.com> <18c3f6e4-84af-87c8-3441-d8b368ade1c8@amd.com> From: Paolo Bonzini Message-ID: <0337f197-a31d-db90-1563-363404298849@redhat.com> Date: Thu, 11 Jan 2018 11:33:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <18c3f6e4-84af-87c8-3441-d8b368ade1c8@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 10/01/2018 21:13, Tom Lendacky wrote: > On 1/9/2018 6:03 AM, Paolo Bonzini wrote: >> Direct access to MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD is important >> for performance. Allow load/store of MSR_IA32_SPEC_CTRL, restore guest >> IBRS on VM entry and set it to 0 on VM exit (because Linux does not use >> it yet). >> >> Signed-off-by: Paolo Bonzini >> --- >> arch/x86/kvm/svm.c | 42 ++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 42 insertions(+) >> >> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c >> index 31ace8d7774a..934a21e02e03 100644 >> --- a/arch/x86/kvm/svm.c >> +++ b/arch/x86/kvm/svm.c > > ... > >> @@ -5015,6 +5045,18 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu) >> #endif >> ); >> >> + if (have_spec_ctrl) { >> + rdmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl); >> + if (svm->spec_ctrl != 0) >> + wrmsrl(MSR_IA32_SPEC_CTRL, 0); >> + } >> + /* >> + * Speculative execution past the above wrmsrl might encounter >> + * an indirect branch and use guest-controlled contents of the >> + * indirect branch predictor; block it. >> + */ >> + asm("lfence"); > > This will end up needing to be an alternative macro based on the > LFENCE_RDTSC or MFENCE_RDTSC features [1]. You'll probably just want to > use the speculation barrier macro that ends up being defined to control > the speculation here. Yes. Though, is there any processor that has spec_ctrl (which is none on AMD) but needs a full fence? Paolo > Thanks, > Tom > > [1] https://marc.info/?l=linux-kernel&m=151545930207815&w=2 > >> + >> #ifdef CONFIG_X86_64 >> wrmsrl(MSR_GS_BASE, svm->host.gs_base); >> #else >>