Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753998AbeAKXKM (ORCPT + 1 other); Thu, 11 Jan 2018 18:10:12 -0500 Received: from vern.gendns.com ([206.190.152.46]:43587 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751621AbeAKXKL (ORCPT ); Thu, 11 Jan 2018 18:10:11 -0500 Subject: Re: [PATCH] clk: divider: fix clk_round_rate() when CLK_DIVIDER_READ_ONLY && CLK_RATE_SET_PARENT To: Stephen Boyd Cc: linux-clk@vger.kernel.org, Michael Turquette , linux-kernel@vger.kernel.org References: <1515262769-22665-1-git-send-email-david@lechnology.com> <20180110220333.GF28313@codeaurora.org> From: David Lechner Message-ID: Date: Thu, 11 Jan 2018 17:10:11 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20180110220333.GF28313@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 01/10/2018 04:03 PM, Stephen Boyd wrote: > On 01/06, David Lechner wrote: >> clk_round_rate() 'answers the question "if I were to pass @rate to >> clk_set_rate(), what clock rate would I end up with?" without changing >> the hardware'. >> >> Currently, clk_divider_round_rate() returns the "current value" when >> divider->flags & CLK_DIVIDER_READ_ONLY. But, if CLK_SET_RATE_PARENT is >> set, then clk_set_rate() is supposed to propagate the rate change to the >> parent clock. So, we need to do check for CLK_SET_RATE_PARENT and if it >> is set, ask the parent clock what rate it can provide given the current >> divider value. >> >> Signed-off-by: David Lechner > > Jerome sent a patch the day before that probably addresses the > same thing. See the message-id of 20180105170959.17266-2-jbrunet@baylibre.com > for more info. > Indeed, thank you. We can drop this patch.