Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932783AbeALAyz (ORCPT + 1 other); Thu, 11 Jan 2018 19:54:55 -0500 Received: from mga01.intel.com ([192.55.52.88]:23328 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932148AbeALAyv (ORCPT ); Thu, 11 Jan 2018 19:54:51 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,346,1511856000"; d="scan'208";a="10599391" Subject: [PATCH v2 02/19] arm64: implement ifence_array_ptr() From: Dan Williams To: linux-kernel@vger.kernel.org Cc: Mark Rutland , linux-arch@vger.kernel.org, kernel-hardening@lists.openwall.com, Peter Zijlstra , Will Deacon , tglx@linutronix.de, torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@linux.intel.com Date: Thu, 11 Jan 2018 16:46:35 -0800 Message-ID: <151571799562.27429.4130452417520177349.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <151571798296.27429.7166552848688034184.stgit@dwillia2-desk3.amr.corp.intel.com> References: <151571798296.27429.7166552848688034184.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.17.1-9-g687f MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: From: Mark Rutland This patch implements ifence_array_ptr() for arm64, using an LDR+CSEL+CSDB sequence to inhibit speculative use of the returned value. Signed-off-by: Mark Rutland Signed-off-by: Will Deacon Cc: Peter Zijlstra Signed-off-by: Dan Williams --- arch/arm64/include/asm/barrier.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 77651c49ef44..74ffcddb26e6 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -40,6 +40,30 @@ #define dma_rmb() dmb(oshld) #define dma_wmb() dmb(oshst) +#define ifence_array_ptr(arr, idx, sz) \ +({ \ + typeof(&(arr)[0]) __nap_arr = (arr); \ + typeof(idx) __nap_idx = (idx); \ + typeof(sz) __nap_sz = (sz); \ + \ + unsigned long __nap_ptr = (unsigned long)__nap_arr + \ + sizeof(__nap_arr[0]) * idx; \ + \ + asm volatile( \ + " cmp %[i], %[s]\n" \ + " b.cs 1f\n" \ + " ldr %[p], %[pp]\n" \ + "1: csel %[p], %[p], xzr, cc\n" \ + " hint #0x14 // CSDB\n" \ + : [p] "=&r" (__nap_ptr) \ + : [pp] "m" (__nap_ptr), \ + [i] "r" ((unsigned long)__nap_idx), \ + [s] "r" ((unsigned long)__nap_sz) \ + : "cc"); \ + \ + (typeof(&(__nap_arr)[0]))__nap_ptr; \ +}) + #define __smp_mb() dmb(ish) #define __smp_rmb() dmb(ishld) #define __smp_wmb() dmb(ishst)