Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933119AbeALBd0 (ORCPT + 1 other); Thu, 11 Jan 2018 20:33:26 -0500 Received: from mga11.intel.com ([192.55.52.93]:45984 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932526AbeALBcY (ORCPT ); Thu, 11 Jan 2018 20:32:24 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,346,1511856000"; d="scan'208";a="10606000" From: Ashok Raj To: linux-kernel@vger.kernel.org, Thomas Gleixner , Tim Chen , Andy Lutomirski , Linus Torvalds , Greg KH Cc: Ashok Raj , Dave Hansen , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , David Woodhouse , Peter Zijlstra , Dan Williams , Paolo Bonzini , Jun Nakajima , Asit Mallick Subject: [PATCH 3/5] x86/ibrs: Add direct access support for MSR_IA32_SPEC_CTRL Date: Thu, 11 Jan 2018 17:32:17 -0800 Message-Id: <1515720739-43819-4-git-send-email-ashok.raj@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515720739-43819-1-git-send-email-ashok.raj@intel.com> References: <1515720739-43819-1-git-send-email-ashok.raj@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Add direct access to MSR_IA32_SPEC_CTRL from a guest. Also save/restore IBRS values during exits and guest resume path. Rebasing based on Tim's patch Signed-off-by: Ashok Raj --- arch/x86/kvm/cpuid.c | 3 ++- arch/x86/kvm/vmx.c | 41 +++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/x86.c | 1 + 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 0099e10..6fa81c7 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -70,6 +70,7 @@ u64 kvm_supported_xcr0(void) /* These are scattered features in cpufeatures.h. */ #define KVM_CPUID_BIT_AVX512_4VNNIW 2 #define KVM_CPUID_BIT_AVX512_4FMAPS 3 +#define KVM_CPUID_BIT_SPEC_CTRL 26 #define KF(x) bit(KVM_CPUID_BIT_##x) int kvm_update_cpuid(struct kvm_vcpu *vcpu) @@ -392,7 +393,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, /* cpuid 7.0.edx*/ const u32 kvm_cpuid_7_0_edx_x86_features = - KF(AVX512_4VNNIW) | KF(AVX512_4FMAPS); + KF(AVX512_4VNNIW) | KF(AVX512_4FMAPS) | KF(SPEC_CTRL); /* all calls to cpuid_count() should be made on the same cpu */ get_cpu(); diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 62ee436..1913896 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -50,6 +50,7 @@ #include #include #include +#include #include "trace.h" #include "pmu.h" @@ -579,6 +580,7 @@ struct vcpu_vmx { u32 vm_entry_controls_shadow; u32 vm_exit_controls_shadow; u32 secondary_exec_control; + u64 spec_ctrl; /* * loaded_vmcs points to the VMCS currently used in this vcpu. For a @@ -3259,6 +3261,9 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_TSC: msr_info->data = guest_read_tsc(vcpu); break; + case MSR_IA32_SPEC_CTRL: + msr_info->data = to_vmx(vcpu)->spec_ctrl; + break; case MSR_IA32_SYSENTER_CS: msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); break; @@ -3366,6 +3371,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_TSC: kvm_write_tsc(vcpu, msr_info); break; + case MSR_IA32_SPEC_CTRL: + to_vmx(vcpu)->spec_ctrl = msr_info->data; + break; case MSR_IA32_CR_PAT: if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) @@ -6790,6 +6798,13 @@ static __init int hardware_setup(void) kvm_tsc_scaling_ratio_frac_bits = 48; } + /* + * If feature is available then setup MSR_IA32_SPEC_CTRL to be in + * passthrough mode for the guest. + */ + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) + vmx_disable_intercept_for_msr(MSR_IA32_SPEC_CTRL, false); + vmx_disable_intercept_for_msr(MSR_FS_BASE, false); vmx_disable_intercept_for_msr(MSR_GS_BASE, false); vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); @@ -9242,6 +9257,15 @@ static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu) vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); } +static void save_guest_spec_ctrl(struct vcpu_vmx *vmx) +{ + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) { + vmx->spec_ctrl = spec_ctrl_get(); + spec_ctrl_restriction_on(); + } else + rmb(); +} + static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); @@ -9298,6 +9322,21 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) vmx_arm_hv_timer(vcpu); vmx->__launched = vmx->loaded_vmcs->launched; + + /* + * Just update whatever the value was set for the MSR in guest. + * If this is unlaunched: Assume that initialized value is 0. + * IRQ's also need to be disabled. If guest value is 0, an interrupt + * could start running in unprotected mode (i.e with IBRS=0). + */ + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) { + /* + * FIXME: lockdep_assert_irqs_disabled(); + */ + WARN_ON_ONCE(!irqs_disabled()); + spec_ctrl_set(vmx->spec_ctrl); + } + asm( /* Store host registers */ "push %%" _ASM_DX "; push %%" _ASM_BP ";" @@ -9403,6 +9442,8 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) #endif ); + save_guest_spec_ctrl(vmx); + /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ if (debugctlmsr) update_debugctlmsr(debugctlmsr); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 03869eb..9ffb9d6 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1006,6 +1006,7 @@ static u32 msrs_to_save[] = { #endif MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, + MSR_IA32_SPEC_CTRL, }; static unsigned num_msrs_to_save; -- 2.7.4