Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964832AbeALQ0F (ORCPT + 1 other); Fri, 12 Jan 2018 11:26:05 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:16529 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934004AbeALQ0D (ORCPT ); Fri, 12 Jan 2018 11:26:03 -0500 From: Philippe Cornu To: Archit Taneja , Andrzej Hajda , Laurent Pinchart , David Airlie , Philippe Cornu , Philipp Zabel , Benjamin Gaignard , Bhumika Goyal , , CC: Yannick Fertre , Vincent Abriou , Alexandre Torgue , "Maxime Coquelin" , Gabriel Fernandez , Ludovic Barre , "Fabien Dessenne" , Mickael Reulier , Brian Norris Subject: [PATCH v2] drm/bridge/synopsys: dsi: add optional pixel clock Date: Fri, 12 Jan 2018 17:25:30 +0100 Message-ID: <20180112162530.31432-1-philippe.cornu@st.com> X-Mailer: git-send-email 2.15.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-01-12_09:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: The pixel clock is optional. When available, it offers a better preciseness for timing computations and allows to reduce the extra dsi bandwidth in burst mode (from ~20% to ~10-12%, hw platform dependent). Signed-off-by: Philippe Cornu --- Changes in v2: Improve px_clk probing in case of ENOENT dt returned value (thanks to Philipp Zabel & Andrzej Hajda comments) drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index c39c7dce20ed..62fcff881b98 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -225,6 +225,7 @@ struct dw_mipi_dsi { void __iomem *base; struct clk *pclk; + struct clk *px_clk; unsigned int lane_mbps; /* per lane */ u32 channel; @@ -753,24 +754,28 @@ void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; void *priv_data = dsi->plat_data->priv_data; + struct drm_display_mode px_clk_mode = *mode; int ret; clk_prepare_enable(dsi->pclk); - ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags, + if (dsi->px_clk) + px_clk_mode.clock = clk_get_rate(dsi->px_clk) / 1000; + + ret = phy_ops->get_lane_mbps(priv_data, &px_clk_mode, dsi->mode_flags, dsi->lanes, dsi->format, &dsi->lane_mbps); if (ret) DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); pm_runtime_get_sync(dsi->dev); dw_mipi_dsi_init(dsi); - dw_mipi_dsi_dpi_config(dsi, mode); + dw_mipi_dsi_dpi_config(dsi, &px_clk_mode); dw_mipi_dsi_packet_handler_config(dsi); dw_mipi_dsi_video_mode_config(dsi); - dw_mipi_dsi_video_packet_config(dsi, mode); + dw_mipi_dsi_video_packet_config(dsi, &px_clk_mode); dw_mipi_dsi_command_mode_config(dsi); - dw_mipi_dsi_line_timer_config(dsi, mode); - dw_mipi_dsi_vertical_timing_config(dsi, mode); + dw_mipi_dsi_line_timer_config(dsi, &px_clk_mode); + dw_mipi_dsi_vertical_timing_config(dsi, &px_clk_mode); dw_mipi_dsi_dphy_init(dsi); dw_mipi_dsi_dphy_timing_config(dsi); @@ -784,7 +789,7 @@ void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, dw_mipi_dsi_dphy_enable(dsi); - dw_mipi_dsi_wait_for_two_frames(mode); + dw_mipi_dsi_wait_for_two_frames(&px_clk_mode); /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ dw_mipi_dsi_set_mode(dsi, 0); @@ -878,6 +883,15 @@ __dw_mipi_dsi_probe(struct platform_device *pdev, return ERR_PTR(ret); } + dsi->px_clk = devm_clk_get(dev, "px_clk"); + if (PTR_ERR(dsi->px_clk) == -ENOENT) { + dsi->px_clk = NULL; + } else if (IS_ERR(dsi->px_clk)) { + ret = PTR_ERR(dsi->px_clk); + dev_err(dev, "Unable to get optional px_clk: %d\n", ret); + dsi->px_clk = NULL; + } + /* * Note that the reset was not defined in the initial device tree, so * we have to be prepared for it not being found. -- 2.15.1