Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934130AbeALRGc (ORCPT + 1 other); Fri, 12 Jan 2018 12:06:32 -0500 Received: from mail-by2nam03on0040.outbound.protection.outlook.com ([104.47.42.40]:25760 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933994AbeALRGa (ORCPT ); Fri, 12 Jan 2018 12:06:30 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Thomas.Lendacky@amd.com; Subject: Re: [PATCH 5/5] x86/feature: Detect the x86 feature Indirect Branch Prediction Barrier To: "Woodhouse, David" , "linux-kernel@vger.kernel.org" , "tim.c.chen@linux.intel.com" , "ashok.raj@intel.com" , "torvalds@linux-foundation.org" , "tglx@linutronix.de" , "luto@kernel.org" , "gregkh@linuxfoundation.org" Cc: "arjan.van.de.ven@intel.com" , "peterz@infradead.org" , "ak@linux.intel.com" , "dan.j.williams@intel.com" , "aarcange@redhat.com" , "pbonzini@redhat.com" , "dave.hansen@intel.com" , "jun.nakajima@intel.com" , "asit.k.mallick@intel.com" References: <1515720739-43819-1-git-send-email-ashok.raj@intel.com> <1515720739-43819-6-git-send-email-ashok.raj@intel.com> <75ceffe7-5035-dbb4-6027-91daa4e7fa94@amd.com> <1515771377.22302.461.camel@amazon.co.uk> From: Tom Lendacky Message-ID: <413ada3b-8cf8-195c-a506-38497adde41a@amd.com> Date: Fri, 12 Jan 2018 11:06:21 -0600 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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I don't want Intel posting > deliberately AMD-ignoring patches. Sort it out, guys. > Based on the current patches, here is what it should be for the standalone IBPB support: x86/cpu: Detect standalone IBPB support From: Tom Lendacky Add support to detect standalone IBPB feature support. This feature is indicated as follows: CPUID EAX=0x80000008, ECX=0x00 return EBX[12] indicates support for IBPB Signed-off-by: Tom Lendacky --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/spec_ctrl.c | 9 +++++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 52f37fc..33f0215 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -273,6 +273,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/arch/x86/kernel/cpu/spec_ctrl.c b/arch/x86/kernel/cpu/spec_ctrl.c index 6cfec19..1aadd73 100644 --- a/arch/x86/kernel/cpu/spec_ctrl.c +++ b/arch/x86/kernel/cpu/spec_ctrl.c @@ -16,12 +16,13 @@ void spec_ctrl_scan_feature(struct cpuinfo_x86 *c) static_branch_enable(&spec_ctrl_dynamic_ibrs); } /* - * For Intel CPU's this MSR is shared the same cpuid - * enumeration. When MSR_IA32_SPEC_CTRL is present - * MSR_IA32_SPEC_CTRL is also available - * TBD: AMD might have a separate enumeration for each. + * The PRED_CMD MSR is shared with the cpuid enumeration + * for SPEC_CTRL. When MSR_IA32_SPEC_CTRL is present, + * then MSR_IA32_PRED_CMD is, too. */ set_cpu_cap(c, X86_FEATURE_PRED_CMD); + } else if (boot_cpu_has(X86_FEATURE_IBPB)) { + set_cpu_cap(c, X86_FEATURE_PRED_CMD); } } > > > Amazon Web Services UK Limited. Registered in England and Wales with > registration number 08650665 and which has its registered office at 60 > Holborn Viaduct, London EC1A 2FD, United Kingdom.