Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965365AbeALXRl (ORCPT + 1 other); Fri, 12 Jan 2018 18:17:41 -0500 Received: from mail-io0-f175.google.com ([209.85.223.175]:33694 "EHLO mail-io0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965236AbeALXRi (ORCPT ); Fri, 12 Jan 2018 18:17:38 -0500 X-Google-Smtp-Source: ACJfBovfJ5dsy1qYUJpwpwuKUC70AE44MsUvnUf2qF4tWv8Om296r5L0xJrD5RbsvRPlq4dtRHtxYZsLj68ElJHNyCg= MIME-Version: 1.0 In-Reply-To: References: <222d0a6b-820f-4d7c-a616-ac89f77c3c09@default> <834e9b46-5d59-a81e-8cda-5f576964e1cb@redhat.com> From: Jim Mattson Date: Fri, 12 Jan 2018 15:17:37 -0800 Message-ID: Subject: Re: [PATCH 3/8] kvm: vmx: pass MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD down to the guest To: Nadav Amit Cc: Paolo Bonzini , Liran Alon , "the arch/x86 maintainers" , dwmw@amazon.co.uk, Borislav Petkov , Anthony Liguori , Tom Lendacky , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , LKML , kvm list Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Nadav, See section 2.5.1.2 (paragraph 3) in https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf. On Tue, Jan 9, 2018 at 9:03 PM, Nadav Amit wrote: > Paolo Bonzini wrote: > >> On 09/01/2018 17:48, Liran Alon wrote: >>>>> + if (have_spec_ctrl) { >>>>> + rdmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl); >>>>> + if (vmx->spec_ctrl != 0) >>>>> + wrmsrl(MSR_IA32_SPEC_CTRL, 0); >>> >>> As I said also on the AMD patch, I think this is a bug. >>> Intel specify that we should set IBRS bit even if it was already set on every #VMExit. >> >> That's correct (though I'd like to understand _why_---I'm not inclined >> to blindly trust a spec), but for now it's saving a wrmsr of 0. That is >> quite obviously okay, and will be also okay after the bare-metal IBRS >> patches. >> >> Of course the code will become something like >> >> if (using_ibrs || vmx->spec_ctrl != 0) >> wrmsrl(MSR_IA32_SPEC_CTRL, host_ibrs); >> >> optimizing the case where the host is using retpolines. > > Excuse my ignorance: Can you point me to the specifications that mention “we > should set IBRS bit even if it was already set on every #VMExit” ? > > Thanks, > Nadav