Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753311AbeAOBBl (ORCPT + 1 other); Sun, 14 Jan 2018 20:01:41 -0500 Received: from mail-io0-f193.google.com ([209.85.223.193]:37228 "EHLO mail-io0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752997AbeAOBBh (ORCPT ); Sun, 14 Jan 2018 20:01:37 -0500 X-Google-Smtp-Source: ACJfBovP8VPIp1Eo7okKwW0m4vPRz8JXDhB5HWQyIVeWgPk/wabBaqEEo3fBc0iAc6INH9xd1HCamQ2UjcOodkbrpxM= MIME-Version: 1.0 In-Reply-To: <1515759368-16946-2-git-send-email-patrice.chotard@st.com> References: <1515759368-16946-1-git-send-email-patrice.chotard@st.com> <1515759368-16946-2-git-send-email-patrice.chotard@st.com> From: Linus Walleij Date: Mon, 15 Jan 2018 02:01:36 +0100 Message-ID: Subject: Re: [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register To: Patrice CHOTARD Cc: Russell King , Ulf Hansson , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Alexandre Torgue , linux-mmc , "linux-kernel@vger.kernel.org" , linux-clk , Linux ARM , linux-gpio@vger.kernel.org, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Andrea Merello Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On Fri, Jan 12, 2018 at 1:15 PM, wrote: > From: Patrice Chotard > > Two mask registers are used in order to select which events have to > actually generate an interrupt on each IRQ line. > > It seems that in the single-IRQ case it's assumed that the IRQs lines > are simply OR-ed, while the two mask registers are still present. The > driver still programs the two mask registers separately. > > However the STM32 variant has only one IRQ, and also has only one mask > register. > > This patch prepares for STM32 variant support by making the driver using > only one mask register. > > This patch also optimize the MMCIMASK1 mask usage by caching it into > host->mask1_reg which avoid to read it into mmci_irq(). > > Tested only on STM32 variant. RFT for variants other than STM32 > > Signed-off-by: Andrea Merello > Signed-off-by: Patrice Chotard Reviewed-by: Linus Walleij Yours, Linus Walleij