Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934073AbeAOF55 (ORCPT + 1 other); Mon, 15 Jan 2018 00:57:57 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:35016 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933934AbeAOF5w (ORCPT ); Mon, 15 Jan 2018 00:57:52 -0500 X-Google-Smtp-Source: ACJfBotGfHjmWGU4sw4GCCkSZcxv8HfzJYh/4203j9Ln6Ih7ZBNsEti8rupxoBK+SSuRoQCYzWpC/g== From: Greentime Hu To: greentime@andestech.com, linux-kernel@vger.kernel.org, arnd@arndb.de, linux-arch@vger.kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, netdev@vger.kernel.org, deanbo422@gmail.com, devicetree@vger.kernel.org, viro@zeniv.linux.org.uk, dhowells@redhat.com, will.deacon@arm.com, daniel.lezcano@linaro.org, linux-serial@vger.kernel.org, geert.uytterhoeven@gmail.com, linus.walleij@linaro.org, mark.rutland@arm.com, greg@kroah.com, ren_guo@c-sky.com, rdunlap@infradead.org, davem@davemloft.net, jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com Cc: Rick Chen , green.hu@gmail.com, rick@andestech.com Subject: [PATCH v6 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer Date: Mon, 15 Jan 2018 13:57:29 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: From: Rick Chen ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again. It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically. Signed-off-by: Rick Chen Signed-off-by: Greentime Hu Reviewed-by: Linus Walleij --- drivers/clocksource/Kconfig | 9 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-atcpit100.c | 244 +++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+) create mode 100644 drivers/clocksource/timer-atcpit100.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cc60620..5014949 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -615,4 +615,13 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config ATCPIT100_TIMER + bool "ATCPIT100 timer driver" + depends on NDS32 || COMPILE_TEST + depends on HAS_IOMEM + select TIMER_OF + default NDS32 + help + This option enables support for the Andestech ATCPIT100 timers. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 72711f1..7403a19 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -75,3 +75,4 @@ obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o +obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o diff --git a/drivers/clocksource/timer-atcpit100.c b/drivers/clocksource/timer-atcpit100.c new file mode 100644 index 0000000..e34b2fe --- /dev/null +++ b/drivers/clocksource/timer-atcpit100.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2005-2017 Andes Technology Corporation +/* + * Andestech ATCPIT100 Timer Device Driver Implementation + * Rick Chen, Andes Technology Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "timer-of.h" + +/* + * Definition of register offsets + */ + +/* ID and Revision Register */ +#define ID_REV 0x0 + +/* Configuration Register */ +#define CFG 0x10 + +/* Interrupt Enable Register */ +#define INT_EN 0x14 +#define CH_INT_EN(c, i) ((1<event_handler(evt); + + return IRQ_HANDLED; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE, + + .clkevt = { + .name = "atcpit100_tick", + .rating = 300, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = atcpit100_clkevt_shutdown, + .set_state_periodic = atcpit100_clkevt_set_periodic, + .set_state_oneshot = atcpit100_clkevt_set_oneshot, + .tick_resume = atcpit100_clkevt_shutdown, + .set_next_event = atcpit100_clkevt_next_event, + .cpumask = cpu_all_mask, + }, + + .of_irq = { + .handler = atcpit100_timer_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, + + /* + * FIXME: we currently only support clocking using PCLK + * and using EXTCLK is not supported in the driver. + */ + .of_clk = { + .name = "PCLK", + } +}; + +static u64 notrace atcpit100_timer_sched_read(void) +{ + return ~readl(timer_of_base(&to) + CH1_CNT); +} + +static int __init atcpit100_timer_init(struct device_node *node) +{ + int ret; + u32 val; + void __iomem *base; + + ret = timer_of_init(node, &to); + if (ret) + return ret; + + base = timer_of_base(&to); + + sched_clock_register(atcpit100_timer_sched_read, 32, + timer_of_rate(&to)); + + ret = clocksource_mmio_init(base + CH1_CNT, + node->name, timer_of_rate(&to), 300, 32, + clocksource_mmio_readl_down); + + if (ret) { + pr_err("Failed to register clocksource\n"); + return ret; + } + + /* clear channel 0 timer0 interrupt */ + atcpit100_timer_clear_interrupt(base); + + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + TIMER_SYNC_TICKS, 0xffffffff); + atcpit100_ch0_tmr0_en(base); + atcpit100_ch1_tmr0_en(base); + atcpit100_clocksource_start(base); + atcpit100_clkevt_time_start(base); + + /* Enable channel 0 timer0 interrupt */ + val = readl(base + INT_EN); + writel(val | CH0INT0EN, base + INT_EN); + + return ret; +} + +TIMER_OF_DECLARE(atcpit100, "andestech,atcpit100", atcpit100_timer_init); -- 1.7.9.5