Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751650AbeAPEDG (ORCPT + 1 other); Mon, 15 Jan 2018 23:03:06 -0500 Received: from mail-vk0-f54.google.com ([209.85.213.54]:36913 "EHLO mail-vk0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751139AbeAPEDF (ORCPT ); Mon, 15 Jan 2018 23:03:05 -0500 X-Google-Smtp-Source: ACJfBottDkwVrMBT7Yvte8KprBffISDimM3zD3d1Wii/MQ8ABo1rJfe0ODrVbr8Pja1eg65G0HJKJA== MIME-Version: 1.0 In-Reply-To: <20180115171614.14474-31-thierry.escande@collabora.com> References: <20180115171614.14474-1-thierry.escande@collabora.com> <20180115171614.14474-31-thierry.escande@collabora.com> From: Tomasz Figa Date: Tue, 16 Jan 2018 13:02:40 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 30/40] drm/rockchip: Flush PSR before committing modeset disables/enables To: Thierry Escande Cc: Archit Taneja , Inki Dae , Thierry Reding , Sandy Huang , Sean Paul , David Airlie , Haixia Shi , =?UTF-8?Q?=C3=98rjan_Eide?= , zain wang , Yakir Yang , Lin Huang , Douglas Anderson , Mark Yao , linux-kernel@vger.kernel.org, "open list:ARM/Rockchip SoC..." , dri-devel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Hi Thierry, On Tue, Jan 16, 2018 at 2:16 AM, Thierry Escande wrote: > From: Tomasz Figa > > Currently PSR flush is triggered from CRTC's .atomic_begin() callback, > which is executed after modeset disables and enables and before plane > updates are committed. Since PSR flush and re-enable can be triggered > asynchronously by external sources (input event, delayed work), it can > race with hardware programming done in the aforementioned stages. > > To avoid the race, we can trigger PSR flush before committing modeset > disables/enables. This also has the advantage of removing some > PSR-specific knowledge from the VOP driver. FYI, this patch was eventually found to still leave few unsolved races and was later replaced with a more comprehensive redesign of Rockchip PSR code. Please refer to the following Chromium patches: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/430429/ https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/436571/ https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/438228/ https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/438229/ <- This one effectively replaces all the code added in this patch. https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/438230/ Best regards, Tomasz