Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751835AbeAPKPm (ORCPT + 1 other); Tue, 16 Jan 2018 05:15:42 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:43908 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750878AbeAPKNA (ORCPT ); Tue, 16 Jan 2018 05:13:00 -0500 From: Alexandre Belloni To: James Hogan , Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , devicetree@vger.kernel.org, Sebastian Reichel , linux-pm@vger.kernel.org Subject: [PATCH v3 2/8] dt-bindings: power: reset: Document ocelot-reset binding Date: Tue, 16 Jan 2018 11:12:34 +0100 Message-Id: <20180116101240.5393-3-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180116101240.5393-1-alexandre.belloni@free-electrons.com> References: <20180116101240.5393-1-alexandre.belloni@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Add binding documentation for the Microsemi Ocelot reset block. Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: Sebastian Reichel Cc: linux-pm@vger.kernel.org Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt new file mode 100644 index 000000000000..1b4213eb3473 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -0,0 +1,14 @@ +Microsemi Ocelot reset controller + +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the +SoC MIPS core. + +Required Properties: + - compatible: "mscc,ocelot-chip-reset" + +Example: + reset@1070008 { + compatible = "mscc,ocelot-chip-reset"; + reg = <0x1070008 0x4>; + }; + -- 2.15.1