Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751577AbeAPPsY (ORCPT + 1 other); Tue, 16 Jan 2018 10:48:24 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:59146 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751404AbeAPPsR (ORCPT ); Tue, 16 Jan 2018 10:48:17 -0500 From: Paul Cercueil To: Ralf Baechle , James Hogan Cc: Maarten ter Huurne , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Paul Cercueil Subject: [PATCH v7 04/14] clk: ingenic: Add code to enable/disable PLLs Date: Tue, 16 Jan 2018 16:47:54 +0100 Message-Id: <20180116154804.21150-5-paul@crapouillou.net> In-Reply-To: <20180116154804.21150-1-paul@crapouillou.net> References: <20180105182513.16248-2-paul@crapouillou.net> <20180116154804.21150-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: This commit permits the PLLs to be dynamically enabled and disabled when their children clocks are enabled and disabled. Signed-off-by: Paul Cercueil Acked-by: Stephen Boyd --- drivers/clk/ingenic/cgu.c | 89 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 74 insertions(+), 15 deletions(-) v2: No change v3: No change v4: No change v5: No change v6: No change v7: No change diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 381c4a17a1fc..56a712c9075f 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -107,9 +107,6 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) if (bypass) return parent_rate; - if (!enable) - return 0; - for (od = 0; od < pll_info->od_max; od++) { if (pll_info->od_encoding[od] == od_enc) break; @@ -153,17 +150,25 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, return div_u64((u64)parent_rate * m, n * od); } -static long -ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate, - unsigned long *prate) +static inline const struct ingenic_cgu_clk_info *to_clk_info( + struct ingenic_clk *ingenic_clk) { - struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info; clk_info = &cgu->clock_info[ingenic_clk->idx]; BUG_ON(clk_info->type != CGU_CLK_PLL); + return clk_info; +} + +static long +ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate, + unsigned long *prate) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); + return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL); } @@ -171,19 +176,14 @@ static int ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { - const unsigned timeout = 100; struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; - const struct ingenic_cgu_clk_info *clk_info; - const struct ingenic_cgu_pll_info *pll_info; + const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); + const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; unsigned long rate, flags; - unsigned m, n, od, i; + unsigned int m, n, od; u32 ctl; - clk_info = &cgu->clock_info[ingenic_clk->idx]; - BUG_ON(clk_info->type != CGU_CLK_PLL); - pll_info = &clk_info->pll; - rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, &m, &n, &od); if (rate != req_rate) @@ -202,6 +202,26 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + writel(ctl, cgu->base + pll_info->reg); + spin_unlock_irqrestore(&cgu->lock, flags); + + return 0; +} + +static int ingenic_pll_enable(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); + const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; + const unsigned int timeout = 100; + unsigned long flags; + unsigned int i; + u32 ctl; + + spin_lock_irqsave(&cgu->lock, flags); + ctl = readl(cgu->base + pll_info->reg); + ctl &= ~BIT(pll_info->bypass_bit); ctl |= BIT(pll_info->enable_bit); @@ -223,10 +243,48 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, return 0; } +static void ingenic_pll_disable(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); + const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; + unsigned long flags; + u32 ctl; + + spin_lock_irqsave(&cgu->lock, flags); + ctl = readl(cgu->base + pll_info->reg); + + ctl &= ~BIT(pll_info->enable_bit); + + writel(ctl, cgu->base + pll_info->reg); + spin_unlock_irqrestore(&cgu->lock, flags); +} + +static int ingenic_pll_is_enabled(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); + const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; + unsigned long flags; + u32 ctl; + + spin_lock_irqsave(&cgu->lock, flags); + ctl = readl(cgu->base + pll_info->reg); + spin_unlock_irqrestore(&cgu->lock, flags); + + return !!(ctl & BIT(pll_info->enable_bit)); +} + static const struct clk_ops ingenic_pll_ops = { .recalc_rate = ingenic_pll_recalc_rate, .round_rate = ingenic_pll_round_rate, .set_rate = ingenic_pll_set_rate, + + .enable = ingenic_pll_enable, + .disable = ingenic_pll_disable, + .is_enabled = ingenic_pll_is_enabled, }; /* @@ -601,6 +659,7 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx) } } else if (caps & CGU_CLK_PLL) { clk_init.ops = &ingenic_pll_ops; + clk_init.flags |= CLK_SET_RATE_GATE; caps &= ~CGU_CLK_PLL; -- 2.11.0