Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751741AbeAPPtL (ORCPT + 1 other); Tue, 16 Jan 2018 10:49:11 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:59146 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751547AbeAPPsY (ORCPT ); Tue, 16 Jan 2018 10:48:24 -0500 From: Paul Cercueil To: Ralf Baechle , James Hogan Cc: Maarten ter Huurne , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: [PATCH v7 12/14] MIPS: JZ4770: Work around config2 misreporting associativity Date: Tue, 16 Jan 2018 16:48:02 +0100 Message-Id: <20180116154804.21150-13-paul@crapouillou.net> In-Reply-To: <20180116154804.21150-1-paul@crapouillou.net> References: <20180105182513.16248-2-paul@crapouillou.net> <20180116154804.21150-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: From: Maarten ter Huurne According to config2, the associativity would be 5-ways, but the documentation states 4-ways, which also matches the documented L2 cache size of 256 kB. Signed-off-by: Maarten ter Huurne Reviewed-by: James Hogan --- arch/mips/mm/sc-mips.c | 9 +++++++++ 1 file changed, 9 insertions(+) v2: No change v3: No change v4: Rebased on top of Linux 4.15-rc5 v5: No change v6: No change v7: No change diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 548acb7f8557..394673991bab 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * MIPS32/MIPS64 L2 cache handling @@ -220,6 +221,14 @@ static inline int __init mips_sc_probe(void) else return 0; + /* + * According to config2 it would be 5-ways, but that is contradicted + * by all documentation. + */ + if (current_cpu_type() == CPU_JZRISC && + mips_machtype == MACH_INGENIC_JZ4770) + c->scache.ways = 4; + c->scache.waysize = c->scache.sets * c->scache.linesz; c->scache.waybit = __ffs(c->scache.waysize); -- 2.11.0