Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751963AbeAQELA (ORCPT + 1 other); Tue, 16 Jan 2018 23:11:00 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:4208 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750868AbeAQEK7 (ORCPT ); Tue, 16 Jan 2018 23:10:59 -0500 Subject: Re: [PATCH v2 07/11] arm64: Add skeleton to harden the branch predictor against aliasing attacks To: Will Deacon , References: <1515157961-20963-1-git-send-email-will.deacon@arm.com> <1515157961-20963-8-git-send-email-will.deacon@arm.com> CC: , , , , , , From: Yisheng Xie Message-ID: <01c224eb-9bec-6b16-7ecf-14837cc107b6@huawei.com> Date: Wed, 17 Jan 2018 12:10:33 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: <1515157961-20963-8-git-send-email-will.deacon@arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.29.40] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Hi Will, On 2018/1/5 21:12, Will Deacon wrote: > diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c > index 5f7097d0cd12..d99b36555a16 100644 > --- a/arch/arm64/mm/context.c > +++ b/arch/arm64/mm/context.c > @@ -246,6 +246,8 @@ asmlinkage void post_ttbr_update_workaround(void) > "ic iallu; dsb nsh; isb", > ARM64_WORKAROUND_CAVIUM_27456, > CONFIG_CAVIUM_ERRATUM_27456)); > + > + arm64_apply_bp_hardening(); > } post_ttbr_update_workaround was used for fix Cavium erratum 2745? so does that means, if we do not have this erratum, we do not need arm64_apply_bp_hardening()? when mm_swtich and kernel_exit? >From the code logical, it seems not only related to erratum 2745 anymore? should it be renamed? Thanks Yisheng