Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753394AbeAQN6y (ORCPT + 1 other); Wed, 17 Jan 2018 08:58:54 -0500 Received: from mx1.redhat.com ([209.132.183.28]:54422 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753363AbeAQN6v (ORCPT ); Wed, 17 Jan 2018 08:58:51 -0500 Subject: Re: [PATCH 2/6] s390: implement nospec_[load|ptr] To: Martin Schwidefsky , linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, kvm@vger.kernel.org Cc: Heiko Carstens , Paolo Bonzini , Cornelia Huck , Greg Kroah-Hartman , Jon Masters , Marcus Meissner , Jiri Kosina References: <1516182519-10623-1-git-send-email-schwidefsky@de.ibm.com> <1516182519-10623-3-git-send-email-schwidefsky@de.ibm.com> From: David Hildenbrand Organization: Red Hat GmbH Message-ID: <08d3bfc0-97ae-6f2b-c44b-531be00737cc@redhat.com> Date: Wed, 17 Jan 2018 14:58:45 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <1516182519-10623-3-git-send-email-schwidefsky@de.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Wed, 17 Jan 2018 13:58:50 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: On 17.01.2018 10:48, Martin Schwidefsky wrote: > Implement nospec_load() and nospec_ptr() for s390 with the new > gmb() barrier between the boundary condition and the load that > may not be done speculatively. > > Acked-by: Christian Borntraeger > Signed-off-by: Martin Schwidefsky > --- > arch/s390/include/asm/barrier.h | 38 ++++++++++++++++++++++++++++++++++++++ > arch/s390/kernel/alternative.c | 7 +++++++ > 2 files changed, 45 insertions(+) > > diff --git a/arch/s390/include/asm/barrier.h b/arch/s390/include/asm/barrier.h > index 1043260..b8836a6 100644 > --- a/arch/s390/include/asm/barrier.h > +++ b/arch/s390/include/asm/barrier.h > @@ -8,6 +8,8 @@ > #ifndef __ASM_BARRIER_H > #define __ASM_BARRIER_H > > +#include > + > /* > * Force strict CPU ordering. > * And yes, this is required on UP too when we're talking > @@ -23,6 +25,42 @@ > > #define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0) > > +static inline void gmb(void) > +{ > + asm volatile( > + ALTERNATIVE("", ".long 0xb2e8f000", 81) > + : : : "memory"); > +} Just to be sure: There are now 2 new facilities: 81 and 82. Is 82 just the virtualization (SIE) support for 81? -- Thanks, David / dhildenb