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[209.132.180.67]) by mx.google.com with ESMTP id h123si4149057pgc.417.2018.01.17.10.15.07; Wed, 17 Jan 2018 10:15:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754545AbeAQSM4 (ORCPT + 99 others); Wed, 17 Jan 2018 13:12:56 -0500 Received: from mail.kernel.org ([198.145.29.99]:54994 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752579AbeAQSMy (ORCPT ); Wed, 17 Jan 2018 13:12:54 -0500 Received: from mail-io0-f173.google.com (mail-io0-f173.google.com [209.85.223.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 65A0D2178D for ; Wed, 17 Jan 2018 18:12:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65A0D2178D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=luto@kernel.org Received: by mail-io0-f173.google.com with SMTP id z6so4815317iob.11 for ; Wed, 17 Jan 2018 10:12:53 -0800 (PST) X-Gm-Message-State: AKwxytfTbgzcG081+JdLMvhDjxIMnjQ4zuT97C1GzlMLy5k1dp+3NYKe /2lZI5qhirsPNhnT3JqInijfnROwU7oYwOriRW7Xow== X-Received: by 10.107.167.136 with SMTP id q130mr12483064ioe.173.1516212772770; Wed, 17 Jan 2018 10:12:52 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.152.114 with HTTP; Wed, 17 Jan 2018 10:12:32 -0800 (PST) In-Reply-To: <20180117141006.GR28161@8bytes.org> References: <1516120619-1159-1-git-send-email-joro@8bytes.org> <1516120619-1159-4-git-send-email-joro@8bytes.org> <20180117092442.GJ28161@8bytes.org> <20180117141006.GR28161@8bytes.org> From: Andy Lutomirski Date: Wed, 17 Jan 2018 10:12:32 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 03/16] x86/entry/32: Leave the kernel via the trampoline stack To: Joerg Roedel Cc: Brian Gerst , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , X86 ML , LKML , Linux-MM , Linus Torvalds , Dave Hansen , Josh Poimboeuf , Juergen Gross , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , David Laight , Denys Vlasenko , Eduardo Valentin , Greg KH , Will Deacon , "Liguori, Anthony" , Daniel Gruss , Hugh Dickins , Kees Cook , Andrea Arcangeli , Waiman Long , Joerg Roedel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 17, 2018 at 6:10 AM, Joerg Roedel wrote: > On Wed, Jan 17, 2018 at 05:57:53AM -0800, Brian Gerst wrote: >> On Wed, Jan 17, 2018 at 1:24 AM, Joerg Roedel wrote: > >> > I have no real idea on how to switch back to the entry stack without >> > access to per_cpu variables. I also can't access the cpu_entry_area for >> > the cpu yet, because for that we need to be on the entry stack already. >> >> Switch to the trampoline stack before loading user segments. > > That requires to copy most of pt_regs from task- to trampoline-stack, > not sure if that is faster than temporily restoring kernel %fs. > I would optimize for simplicity, not speed. You're already planning to write to CR3, which is serializing, blows away the TLB, *and* takes the absurdly large amount of time that the microcode needs to blow away the TLB. (For whatever reason, Intel doesn't seem to have hardware that can quickly wipe the TLB. I suspect that the actual implementation does it in a loop and wipes little pieces at a time. Whatever it actually does, the CR3 write itself is very slow.)