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[209.132.180.67]) by mx.google.com with ESMTP id d74si4980360pfj.265.2018.01.17.13.46.41; Wed, 17 Jan 2018 13:46:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=PV26PgGb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753211AbeAQVqI (ORCPT + 99 others); Wed, 17 Jan 2018 16:46:08 -0500 Received: from mail-pf0-f172.google.com ([209.85.192.172]:43296 "EHLO mail-pf0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752250AbeAQVqG (ORCPT ); Wed, 17 Jan 2018 16:46:06 -0500 Received: by mail-pf0-f172.google.com with SMTP id y26so4913614pfi.10 for ; Wed, 17 Jan 2018 13:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=2t+UTjN1Z7VMf/e1rKxYgteyDGeSHeN+alzTkVmMQwg=; b=PV26PgGbZ1F7gSyazTa2c7vGJLxpBhl3aY3nHq3k+YHr9dhtCxz7kSTiTJOb/CitrI 5DuSCaQMN/mtt0AtQjpW7p/lZ1tYwE2jSByY9cFKr3Gd17Ult2qioLVcskPRUSdL6gO/ TdSjjL+fP6q0EWeK4w78s6awg8fXQVRVqNAuo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=2t+UTjN1Z7VMf/e1rKxYgteyDGeSHeN+alzTkVmMQwg=; b=HfF0nu/eXC5Q4Z4yuwxcPF9ctCFWbRNaWseROn84Kwax27BeUXV2Pk2ongVuud7b+i mQsW44Sd1u1gIeFphlrps1zL3Siy9s4BGV57TCHWiQJxRQVEP2g6NpAmzYEUx7WGnTBo rxfi9ZuEfk2n7L9mK5vnvIpr8TU5HF8Y+X6uREfJPNbmaPYT9u+xa5FDKrVh33el9wVI 9sTJUgQnLvBaW5QbGgmMMq7XOzITI2PKJ5b9DP/209Is1BxUfDSsWtzroTKg6I6mA9Uw 6lXcm5I+dADbhZiQCzdOLD2YBjUgUG95R3nxTimRXZYcSRi48dqhnaYW92sNfCLpH5mq jS3w== X-Gm-Message-State: AKwxyteDd9ggCQ+mdupgC4It+PlAePyDhJbiQJCTtkf3Pzoe6oxcDDNX mfn4rXhy+WXXomGtVbcASPeP5w== X-Received: by 10.99.95.20 with SMTP id t20mr12311760pgb.79.1516225565856; Wed, 17 Jan 2018 13:46:05 -0800 (PST) Received: from google.com ([2620:0:1000:1600:65f5:ad61:66a7:2f6]) by smtp.gmail.com with ESMTPSA id j23sm10244514pfj.42.2018.01.17.13.46.04 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 17 Jan 2018 13:46:05 -0800 (PST) Date: Wed, 17 Jan 2018 13:46:03 -0800 From: Brian Norris To: William Wu Cc: balbi@kernel.org, gregkh@linuxfoundation.org, heiko@sntech.de, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, frank.wang@rock-chips.com, huangtao@rock-chips.com, dianders@google.com, groeck@google.com, daniel.meng@rock-chips.com, John.Youn@synopsys.com, lin.huang@rock-chips.com Subject: Re: [PATCH] usb: dwc3: core: power on PHYs before initializing core Message-ID: <20180117214601.GA111796@google.com> References: <1515729616-8639-1-git-send-email-william.wu@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1515729616-8639-1-git-send-email-william.wu@rock-chips.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 12, 2018 at 12:00:16PM +0800, William Wu wrote: > The dwc3_core_init() gets the PHYs and initializes the PHYs with > the usb_phy_init() and phy_init() functions before initializing > core, and power on the PHYs after core initialization is done. > > However, some platforms (e.g. Rockchip RK3399 DWC3 with Type-C > USB3 PHY), it needs to do some special operation while power on > the Type-C PHY before initializing DWC3 core. It's because that > the RK3399 Type-C PHY requires to hold the DWC3 controller in > reset state to keep the PIPE power state in P2 while configuring > the Type-C PHY, otherwise, it may cause waiting for the PIPE ready > timeout. In this case, if we power on the PHYs after the DWC3 core > initialization is done, the core will be reset to uninitialized > state after power on the PHYs. > > Fix this by powering on the PHYs before initializing core. And > because the GUID register may also be reset in this case, so we > need to configure the GUID register after powering on the PHYs. > > Signed-off-by: William Wu This kinda should be part of your series: [PATCH 0/3] Reset USB3 controller before initializing Type-C PHY on rk3399 or at least mentioned there, because the series there doesn't quite right otherwise, no? Anyway, I think this patch looks OK. I don't immediately see good reasons for delaying the PHY init until later, and I do see reasons why it could be useful earlier: Reviewed-by: Brian Norris > --- > drivers/usb/dwc3/core.c | 46 ++++++++++++++++++++++------------------------ > 1 file changed, 22 insertions(+), 24 deletions(-)