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Date:   Thu, 18 Jan 2018 11:53:23 +0100
From:   Maxime Ripard <maxime.ripard@free-electrons.com>
To:     Jernej Skrabec <jernej.skrabec@siol.net>
Cc:     airlied@linux.ie, robh+dt@kernel.org, mark.rutland@arm.com,
        wens@csie.org, architt@codeaurora.org, a.hajda@samsung.com,
        Laurent.pinchart@ideasonboard.com, mturquette@baylibre.com,
        sboyd@codeaurora.org, Jose.Abreu@synopsys.com,
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        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-sunxi@googlegroups.com
Subject: Re: [PATCH v3 01/12] clk: sunxi-ng: Mask nkmp factors when setting
 register
Message-ID: <20180118105323.fk65vo42eyc6dbzz@flea.lan>
References: <20180117201421.25954-1-jernej.skrabec@siol.net>
 <20180117201421.25954-2-jernej.skrabec@siol.net>
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On Wed, Jan 17, 2018 at 09:14:10PM +0100, Jernej Skrabec wrote:
> Currently, if one of the factors isn't present, bit 0 gets always set to
> 1. For example, A83T has NMP PLLs modelled as NKMP PLL without K. Since
> K is not specified, it's offset, width and shift is 0. Driver assumes
> that lowest value possible is 1, otherwise we would get division by 0.
> That situation causes that bit 0 is always set, which may change wanted
> clock rate.
>=20
> Fix that by masking every factor according to it's specified width.
> Factors with width set to 0 won't have any influence to final register
> value.
>=20
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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