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[209.132.180.67]) by mx.google.com with ESMTP id 20si6128303pge.600.2018.01.18.06.59.13; Thu, 18 Jan 2018 06:59:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=VXXUmGkA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756019AbeARNFl (ORCPT + 99 others); Thu, 18 Jan 2018 08:05:41 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:45005 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755377AbeARNFV (ORCPT ); Thu, 18 Jan 2018 08:05:21 -0500 Received: by mail-wm0-f67.google.com with SMTP id t74so21969080wme.3 for ; Thu, 18 Jan 2018 05:05:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=subject:to:cc:references:from:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=zMwT1cH6c/nCK/BIUjAOs/3cNpExAgIcLMzEIDI4TsE=; b=VXXUmGkAoRVj/AN+GDgcjEJ74yGs4oF4Fg/vxuR0Tr43R/mSyLrgVjd9cwvlqjdKAn oMNz/2Vtsgpc7I5RwHDpJFKb+y3KkyKSEMTCsFeeQUfPw8rmwjNRPrMzI4l9/gQUjxWp GMRPmgC9C9NHq5wz6qioDkCQVVwCSFIfe8nX48dgy5jvTRulhfohfllli1h5/QuQj1QQ rsZIabw9qMn6gtFiMCOc4D6we+QPpPDSoVhIDm8EQztn1Kgkg11S4JIVDKgq6B1AAARM Fi5Z+cyzHpTVo18pUtm5E7raPDqVFk8Qyx4ygNEsIVTsIYPi8wgHHn9suRd7YIzHosH0 DE3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=zMwT1cH6c/nCK/BIUjAOs/3cNpExAgIcLMzEIDI4TsE=; b=DDvb47bDjVwSZ9FZ2YYJt/2UsKNHRy1+wwkZz9wxwSYfVGVyRC10L4LXb9Q8ggKfYz jj+I5zJ9G4Zzo4VksmobjfozyX7qSgpPOWSZqOniZhk8fL2+QY2pVZ2tmmxTAKE4a56F TmbseOaqGnyR4D2dOOeu7tBKr0CzsUZuHTPFHznHM5g/FDMlyW5CwGfPdOFLZE4UGgHH 8TN4nF7yPjN24EUPWI6QXTtRKK4scHJIJt5I+p0E++quGY1fOhFyY7a8Q/k9INg0Ev6l /6u14MaTitq5ZRptmUJa5G4T9jINPk5rjyFhOcRk8bOzoBjV5CXee/JtrUgciD40pNa/ rpNw== X-Gm-Message-State: AKwxyteUJz8i+rfEBLncDQBrP1FyajxBIehIHeQ8KaBdGFutNsu0Lg93 Gd/c5i8L0Hx0UlmMO75APv2p6g== X-Received: by 10.80.138.65 with SMTP id i59mr7926396edi.140.1516280719933; Thu, 18 Jan 2018 05:05:19 -0800 (PST) Received: from [10.1.2.12] ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id h20sm4562358edh.35.2018.01.18.05.05.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Jan 2018 05:05:19 -0800 (PST) Subject: Re: [PATCH v3 04/12] drm/bridge/synopsys: dw-hdmi: Export some PHY related functions To: Jernej Skrabec , maxime.ripard@free-electrons.com, airlied@linux.ie, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, architt@codeaurora.org, a.hajda@samsung.com, Laurent.pinchart@ideasonboard.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, Jose.Abreu@synopsys.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com References: <20180117201421.25954-1-jernej.skrabec@siol.net> <20180117201421.25954-5-jernej.skrabec@siol.net> From: Neil Armstrong Organization: Baylibre Message-ID: Date: Thu, 18 Jan 2018 14:05:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20180117201421.25954-5-jernej.skrabec@siol.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/01/2018 21:14, Jernej Skrabec wrote: > Parts of PHY code could be useful also for custom PHYs. For example, > Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY > with few additional memory mapped registers, so most of the Synopsys PHY > related code could be reused. > > Functions exported here are actually not specific to Synopsys PHYs but > to DWC HDMI controller PHY interface. This means that even if the PHY is > completely custom, i.e. not designed by Synopsys, exported functions can > be useful. > > Reviewed-by: Laurent Pinchart > Signed-off-by: Jernej Skrabec > --- > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 44 +++++++++++++++++++++---------- > drivers/gpu/drm/meson/meson_dw_hdmi.c | 8 +++--- > include/drm/bridge/dw_hdmi.h | 11 ++++++++ > 3 files changed, 45 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > index 7ca14d7325b5..7d80f4b56683 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > @@ -1037,19 +1037,21 @@ static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) > HDMI_PHY_CONF0_SVSRET_MASK); > } > > -static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) > +void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) > { > hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, > HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, > HDMI_PHY_CONF0_GEN2_PDDQ_MASK); > } > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); > > -static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) > +void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) > { > hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, > HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, > HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); > } > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); > > static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) > { > @@ -1065,6 +1067,22 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) > HDMI_PHY_CONF0_SELDIPIF_MASK); > } > > +void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) > +{ > + /* PHY reset. The reset signal is active high on Gen2 PHYs. */ > + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); > + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); > +} > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); > + > +void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) > +{ > + hdmi_phy_test_clear(hdmi, 1); > + hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); > + hdmi_phy_test_clear(hdmi, 0); > +} > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); > + > static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) > { > const struct dw_hdmi_phy_data *phy = hdmi->phy.data; > @@ -1203,16 +1221,11 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi) > if (phy->has_svsret) > dw_hdmi_phy_enable_svsret(hdmi, 1); > > - /* PHY reset. The reset signal is active high on Gen2 PHYs. */ > - hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); > - hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); > + dw_hdmi_phy_reset(hdmi); > > hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); > > - hdmi_phy_test_clear(hdmi, 1); > - hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, > - HDMI_PHY_I2CM_SLAVE_ADDR); > - hdmi_phy_test_clear(hdmi, 0); > + dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); > > /* Write to the PHY as configured by the platform */ > if (pdata->configure_phy) > @@ -1251,15 +1264,16 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) > dw_hdmi_phy_power_off(hdmi); > } > > -static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, > - void *data) > +enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, > + void *data) > { > return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? > connector_status_connected : connector_status_disconnected; > } > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); > > -static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, > - bool force, bool disabled, bool rxsense) > +void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, > + bool force, bool disabled, bool rxsense) > { > u8 old_mask = hdmi->phy_mask; > > @@ -1271,8 +1285,9 @@ static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, > if (old_mask != hdmi->phy_mask) > hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); > } > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); > > -static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) > +void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) > { > /* > * Configure the PHY RX SENSE and HPD interrupts polarities and clear > @@ -1291,6 +1306,7 @@ static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) > hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), > HDMI_IH_MUTE_PHY_STAT0); > } > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); > > static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { > .init = dw_hdmi_phy_init, > diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c > index 17de3afd98f6..e8c3ef8a94ce 100644 > --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c > +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c > @@ -302,7 +302,7 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi, > } > } > > -static inline void dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi) > +static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *dw_hdmi) > { > struct meson_drm *priv = dw_hdmi->priv; > > @@ -409,9 +409,9 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, > msleep(100); > > /* Reset PHY 3 times in a row */ > - dw_hdmi_phy_reset(dw_hdmi); > - dw_hdmi_phy_reset(dw_hdmi); > - dw_hdmi_phy_reset(dw_hdmi); > + meson_dw_hdmi_phy_reset(dw_hdmi); > + meson_dw_hdmi_phy_reset(dw_hdmi); > + meson_dw_hdmi_phy_reset(dw_hdmi); > > /* Temporary Disable VENC video stream */ > if (priv->venc.hdmi_use_enci) > diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h > index 182f83283e24..f3f3f0e1b2d3 100644 > --- a/include/drm/bridge/dw_hdmi.h > +++ b/include/drm/bridge/dw_hdmi.h > @@ -157,7 +157,18 @@ void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); > void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); > > /* PHY configuration */ > +void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); > void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, > unsigned char addr); > > +void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); > +void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); > +void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); > + > +enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, > + void *data); > +void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, > + bool force, bool disabled, bool rxsense); > +void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); > + > #endif /* __IMX_HDMI_H__ */ > Reviewed-by: Neil Armstrong