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From:   Arnd Bergmann <arnd@arndb.de>
Date:   Thu, 18 Jan 2018 17:43:45 +0100
Message-ID: <CAK8P3a06eYpND7mWzUkkABN5xbvzg4ORyPdfUktkEm6-fPyEzg@mail.gmail.com>
Subject: Re: Use arm64's scheme for registering first-level IRQ handlers on RISC-V
To:     Palmer Dabbelt <palmer@sifive.com>
Cc:     Christoph Hellwig <hch@infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        patches@groups.riscv.org
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On Thu, Jan 18, 2018 at 4:40 PM, Palmer Dabbelt <palmer@sifive.com> wrote:
> This patch set has been sitting around for a while, but it got a bit lost in
> the shuffle.  In RISC-V land we currently couple do_IRQ (the C entry point for
> interrupt handling) to our first-level interrupt controller.  While this isn't
> completely crazy (as the first-level interrupt controller is specified by the
> ISA), it is a bit awkward.
>
> This patch set decouples our trap handler from our first-level IRQ chip driver
> by copying what a handful of other architectures are doing.  This does add an
> additional load to the interrupt handling path, but there's a handful of
> performance problems in there that I've been meaning to look at so I don't mind
> adding another one for now.  The advantage is that our irqchip driver is
> decoupled from our arch port, at least at compile time.

Yes, this sounds like a useful cleanup. I also agree with all of Christoph's
suggestions, otherwise it looks good to me.

       Arnd