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[209.132.180.67]) by mx.google.com with ESMTP id 19si7384387pfa.273.2018.01.18.09.48.15; Thu, 18 Jan 2018 09:48:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=IbuqdBgD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755407AbeARRrz (ORCPT + 99 others); Thu, 18 Jan 2018 12:47:55 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:44723 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755084AbeARRrx (ORCPT ); Thu, 18 Jan 2018 12:47:53 -0500 Received: by mail-pg0-f68.google.com with SMTP id m20so14838342pgc.11 for ; Thu, 18 Jan 2018 09:47:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=NUcz+27jM5tCmwc549Ys506yTVbSDOMfnHYGsTo/aCw=; b=IbuqdBgD7EdKPaE5OJ/faa+2GUFqS/mONjK5dpqrX//dZPlsk9cnR2G6uxIhUmrBcj sOzjIIEPk/ozka6idDmvNH++c8ooAGRd5AYK/Rix0ZEjRdpTTMZpBgRoUseN5ffai2dz /R3k60FuNF0xQCWYqLDBMxCYmDgElzR29PsKc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=NUcz+27jM5tCmwc549Ys506yTVbSDOMfnHYGsTo/aCw=; b=ITJWgVeVDFsG2XoGMtnFqvgXNs0GK9Kt7T42VIfgq4bu9vjbX5k7vooXTgVyONH2My ckHcpfNm63L7pGg+X9qkkQqt+I/0w8sfvunNZyibOxE5SXNMx/3CHCoZH1hENskbpSv8 7cKkFHQkOL2ZVcsVsVYVT2X3Tx5+tQfb/QISC+YujNjwQgVXpPSxmmFJol0QI9rMf2Gq cfX7bUnGKed2WyQiRtoEMHMrdqWX9Bgd6y6vAADVn1PdsLqGdAkMF3jCTr2eNcbuvSTl y77Ey0gSdiZGkGqjuu9pr84R/rARXtqLb/GStqKKdbG5ZcgFzVGukVjQvmS2+/dcofTq zyWQ== X-Gm-Message-State: AKwxytfcNddydMHMuwkpUz6OvrxG9hHyxcdpgxl6Tg4YqHKp7H4wC678 QLL7G7mxPI7mTLkQyTMQKzaAOg== X-Received: by 10.99.164.25 with SMTP id c25mr1516208pgf.430.1516297672907; Thu, 18 Jan 2018 09:47:52 -0800 (PST) Received: from google.com ([2620:0:1000:1600:9d81:9e11:38a6:dd73]) by smtp.gmail.com with ESMTPSA id x14sm12287021pgq.43.2018.01.18.09.47.51 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Thu, 18 Jan 2018 09:47:52 -0800 (PST) Date: Thu, 18 Jan 2018 09:47:50 -0800 From: Brian Norris To: Enric Balletbo Serra Cc: William Wu , Kishon Vijay Abraham I , Rob Herring , Heiko =?iso-8859-1?Q?St=FCbner?= , linux-kernel , "open list:ARM/Rockchip SoC..." , Linux ARM , "devicetree@vger.kernel.org" , Frank Wang , huangtao@rock-chips.com, Doug Anderson , Guenter Roeck , daniel.meng@rock-chips.com, John.Youn@synopsys.com, lin.huang@rock-chips.com, Enric Balletbo i Serra Subject: Re: [PATCH 1/3] dt-bindings: phy: phy-rockchip-typec: add usb3 otg reset Message-ID: <20180118174748.GA63108@google.com> References: <1515751704-13213-1-git-send-email-william.wu@rock-chips.com> <1515751704-13213-2-git-send-email-william.wu@rock-chips.com> <20180117220715.GA112833@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 18, 2018 at 06:20:09PM +0100, Enric Balletbo Serra wrote: > As Brian said commit 06c47e6286d5 'usb: dwc3: of-simple: Add support > to get resets for the device' introduced the support to get the resets > from dwc3-of-simple and the queued commit 'b7e63d95c14d arm64: dts: > rockchip: add reset property for dwc3 controllers on rk3399' started > using it. Without the latest I get errors like this doing bind/unbind > tests. > > dwc3: probe of fe900000.dwc3 failed with error -110 > > I just tested these series on top of mainline, I reverted my patch > because otherwise two drivers are requesting the same reset and fails, > and I did some of the bind/unbind test. They just worked fine, and > seems that this is right way, so this makes me think some questions. Actually, this was intended to coexist with DWC3 optionally controlling the same reset. It was written before the reset framework was rewritten to have shared and exclusive resets. Should this be rewritten to use shared resets? We'd have to modify both dwc3 core and the PHY driver. > Should 'b7e63d95c14d arm64: dts: rockchip: add reset property for dwc3 > controllers on rk3399' removed for 4.16? That's a question for Heiko I > guess, if it's removed we will have usb broken meanwhile these patches > doesn't land. If we don't remove the patch we will need to introduce a > new patch in this series that reverts the first patch. If we don't make this shared, I suppose Rockchip should rewrite this series and rebase on Heiko's tree, where the DTSI change should just remove the reset from DWC3 and add it to the PHY node at the same time. That would be an atomic, non-breaking change. > Is commit 06c47e6286d5 'usb: dwc3: of-simple: Add support to get > resets for the device' really needed ? Seems that I was the only user > of it. I don't personally know the history of this one. I just noticed that you started using it to resolve a problem that was implemented differently in our downstream tree. > Anyway, these patches looks good to me and are > > Tested-by: Enric Balletbo i Serra Awesome. Brian