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a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=R/aJbyho09K8T/MJxBeNSbEJ7g3ezHdwFcPxIoiddt8=; b=ki12W0OzXFCjFkveW7AmfWSAIKtgMGVC1H41pzoZYMPqrAow3Xf64t8E4CY8USAslRMhahE/1FhUSBRNc6SmboDXgu4vwmTJPQfrnY/odUbRlefNfUpDEaRozHgReS7X5/lyJfMnbc1NOPG3tUyXy2FNQAU+Gnf8b/GKOccoeEk= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jayachandran.Nair@cavium.com; Received: from jc-sabre (50.233.148.156) by SN2PR0701MB1071.namprd07.prod.outlook.com (2a01:111:e400:341f::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.407.7; Thu, 18 Jan 2018 17:56:20 +0000 Date: Thu, 18 Jan 2018 09:56:16 -0800 From: Jayachandran C To: Will Deacon Cc: Jon Masters , marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, labbott@redhat.com, christoffer.dall@linaro.org Subject: Re: [PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2 Message-ID: <20180118175615.GF38392@jc-sabre> References: <20180108164651.GQ25869@arm.com> <1515502022-7376-1-git-send-email-jnair@caviumnetworks.com> <20180116234554.GA38392@jc-sabre> <20180118135354.GB20783@arm.com> MIME-Version: 1.0 Content-Type: text/plain; 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The approach is similar to the one used for > > > > Cortex-A CPUs, but in case of ThunderX2 we add another SMC call to > > > > test if the firmware supports the capability. > > > > > > > > If the secure firmware has been updated with the mitigation code to > > > > invalidate the branch target buffer, we use the PSCI version call to > > > > invoke it. > > > > > > What's the status of this patch currently? Previously you had suggested > > > to hold while the SMC got standardized, but then you seemed happy with > > > pulling in. What's the latest? > > > > My understanding is that the SMC standardization is being worked on > > but will take more time, and the KPTI current patchset will go to > > mainline before that. > > > > Given that, I would expect arm64 maintainers to pick up this patch for > > ThunderX2, but I have not seen any comments so far. > > > > Will/Marc, please let me know if you are planning to pick this patch > > into the KPTI tree. > > Are you really sure you want us to apply this? If we do, then you can't run > KVM guests anymore because your IMPDEF SMC results in an UNDEF being > injected (crash below). > > I really think that you should just hook up the enable_psci_bp_hardening > callback like we've done for the Cortex CPUs. We can optimise this later > once the SMC standarisation work has been completed (which is nearly final > now and works in a backwards-compatible manner). I think Marc's patch here: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=kvm-arm64/kpti&id=d35e77fae4b70331310c3bc1796bb43b93f9a85e handles returning for undefined smc calls in guest. I think in this case we have to choose between crashing or giving a false sense of security when a guest compiled with HARDEN_BRANCH_PREDICTOR is booted on an hypervisor that does not support hardening. Crashing maybe a reasonable option. JC.